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參數資料
| 型號： | AD9923A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器與V - Driver和精確定時⑩發生器 |
| 文件頁數： | 34/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923A |
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AD9923A
Rev. 0 | Page 34 of 88
VD
REGION 0
FIELD SETTINGS:
1. SEQUENCE CHANGE POSITIONS (SCP1 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD.
2. VSEQSEL0 TO VSEQSEL8 SELECTS THE DESIRED V-SEQUENCE FOR EACH REGION.
3. SGLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD CONTAINS THE SENSOR-GATE PULSE(S).
XV1 TO XV13
HD
SCP 1
SCP 2
VSEQSEL0
VSEQSEL1
SCP 3
VSEQSEL2
SCP 4
VSEQSEL3
SCP 5
VSEQSEL4
SCP 8
VSEQSEL8
REGION 1
REGION 2
REGION 3
REGION 4
REGION 8
VSG
SGACTLINE
SCP 0
0
Figure 46. Complete Field Is Divided into Regions
Second V-Pattern Group During VSG Active Line and
Special V-Pattern Insertion
Most CCDs require additional vertical timing during the sensor
gate line. The AD9923A can output a second V-pattern group
for XV1 to XV13 during the line when the VSG1 to VSG8
sensor gates are active. Figure 47 shows a typical VSG line,
which includes two sets of V-pattern groups for XV1 to XV13.
At the start of the VSG line, the V-pattern group is selected
using the appropriate VSEQSEL register. The second V-pattern
group, unique to the VSG line, is selected using the VPATSECOND
register, located in the field registers. The start position of the
second VPAT group uses the VSTARTSECOND register. For
more information, see Table 16.
In addition to inserting a second V-pattern into the VSG line,
the AD9923A can insert a second V-pattern into any other
single line in each sequence. To enable this function in a par-
ticular sequence, set the SPXV_EN register in the appropriate
set of sequence registers to 1. The SPXV_ACT register determines
the active line for the special second V-pattern. The VPATSELB
and VSTARTB registers control both the V-pattern used and the
starting pixel location of the special second V-pattern. For more
information, see Table 17.
To avoid undesired behavior, do not use the special second
V-pattern in the VSG line; use the existing VPATSECOND and
VSTARTSECOND registers to insert a second V-pattern into
the VSG line. It is recommended that VPATSECOND and
VSTARTSECOND registers are used to create complex timing in
the sensor gate line and not the GROUPB registers. Additionally,
given that the special second V-pattern insertion uses some of the
Group B registers, the user cannot use the special second V-pattern
insertion function and Group B in the same sequence.
Table 17. Special Second V-Pattern Insertion
Length
(Bits)
Range
SPXV_EN
1
0 or 1
Register
Description
0 = off, 1= enable special
second V-pattern insertion.
Active line for special
second V-pattern insertion.
Selected V-pattern for
special second V-pattern
insertion if SPXV_EN = 1.
Start position for selected
V-pattern for special
second V-pattern
insertion if SPXV_EN = 1.
SPXV_ACT
12
Line 0 to
Line 4095
0 to 31
V-pattern
number
0 to 8191
pixel
location
VPATSELB
5
VSTARTB
13
Sweep Mode Operation
The AD9923A contains an additional mode of vertical timing
operation called sweep mode. This mode is used to generate a
large number of repetitive pulses that span across multiple HD
lines. Normally, the vertical timing of the AD9923A must be
contained within one HD line length, but when sweep mode is
enabled, the HD boundaries are ignored until the region is
finished. This is useful, for example, in CCD readout operations.
Depending on the vertical resolution of the CCD, up to 3000 clock
cycles, spanning across several HD line lengths, can be required
to shift charge out of the vertical interline CCD registers. These
registers must be free of all charge at the end of the image
exposure before the image is transferred. This can be accom-
plished in sweep mode by quickly shifting out any charge using
a long series of pulses from the XV1 to XV13 outputs. To enable
sweep mode in any region, program the appropriate SWEEP
register to high.
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