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參數(shù)資料
| 型號： | AD9923ABBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 13/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923ABBCZRL |
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AD9923A
THEORY OF OPERATION
Figure 14 shows the typical system block diagram for the
AD9923A in master mode. The CCD output is processed by
the AD9923A AFE circuitry, which consists of a CDS, VGA,
black level clamp, and ADC. The digitized pixel information is
sent to the digital image processor chip that performs the post-
processing and compression. To operate the CCD, CCD timing
parameters are programmed into the AD9923A from the system
microprocessor through the 3-wire serial interface. The AD9923A
generates the CCD horizontal, vertical, and the internal AFE
clocks from the system Master Clock CLI. The CLI is provided
by the image processor or external crystal. External synchroniza-
tion is provided by a sync pulse from the microprocessor, which
resets internal counters and resyncs the VD and HD outputs.
Rev. 0 | Page 13 of 88
Alternatively, the AD9923A can be operated in slave mode, in
which the VD and HD are provided externally from the image
processor. In this mode, the AD9923A timing is synchronized
with VD and HD.
The H-drivers for HL, H1 to H4, and RG are included in the
AD9923A, allowing these clocks to be directly connected to the
CCD. An H-driver voltage, HVDD, of up to 3.3 V is supported.
An external V-driver is required for the vertical transfer clocks,
the sensor gate pulses, and the substrate clock.
The AD9923A also includes programmable MSHUT and
STROBE outputs that can be used to trigger mechanical shutter
and strobe (flash) circuitry.
Figure 15 and Figure 16 show the maximum horizontal and
vertical counter dimensions for the AD9923A. Internal hori-
zontal and vertical clocking is controlled by these counters to
specify line and pixel locations. The maximum HD length is
8192 pixels per line, and the maximum VD length is 4096 lines
per field.
CCDIN
MSHUT
STROBE
HL, H1 TO H4, RG, VSUB
V1 TO V13, SUBCK
CCD
AD9923A
AFETG +
V-DRIVER
DIGITAL
IMAGE
PROCESSING
ASIC
D[0:11]
DCLK
HD, VD
CLI
SERIAL
INTERFACE
SYNC
MICRO-
PROCESSOR
0
Figure 14. Typical System Block Diagram, Master Mode
13-BIT HORIZONTAL = 8192 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
MAXIMUM
COUNTER
DIMENSIONS
0
Figure 15. Vertical and Horizontal Counters
VD
HD
MAX VD LENGTH IS 4096 LINES
CLI
MAX HD LENGTH IS 8192 PIXELS
0
Figure 16. Maximum VD/HD Dimensions
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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