- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373970 > AD9923ABBCZRL (ANALOG DEVICES INC) CCD Signal Processor with V-Driver and Precision Timing⑩ Generator PDF資料下載
參數(shù)資料
| 型號： | AD9923ABBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 57/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923ABBCZRL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當(dāng)前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
AD9923A
Optical Black Clamp
The optical black clamp loop removes residual offsets in the
signal chain and tracks low frequency variations in the CCD
black level. During the optical black (shielded) pixel interval on
each line, the ADC output is compared with a fixed black level
reference, selected by the user in the CLAMPLEVEL register.
The value can be programmed between 0 LSB and 255 LSB in
1023 steps. The resulting error signal is filtered to reduce noise
and the correction value is applied to the ADC input through a
DAC. Normally, the optical black clamp loop is turned on once
per horizontal line, but this loop can be updated more slowly to
suit a particular application. If external digital clamping is used
during postprocessing, the AD9923A optical black clamping
can be disabled using the CLPENABLE register (Address 0x00,
Bit D2). Even though the loop is disabled, the CLAMPLEVEL
register can still be used to provide programmable offset
adjustment.
Rev. 0 | Page 57 of 88
The CLPOB pulse should be placed during the CCD optical
black pixels. It is recommended that the CLPOB pulse duration
is at least 20 pixels wide to minimize clamping noise. Shorter
pulse widths can be used, but clamping noise might increase,
reducing the ability to track low frequency variations in the
black level. See the Horizontal Clamping and Blanking section
for timing examples.
Digital Data Outputs
The digital output data is latched using the DOUTPHASE
register value, as shown in Figure 73. Output data timing is shown
in Figure 21 and Figure 22. It is also possible to leave the output
latches transparent, so that the data outputs from the ADC are
immediately valid. Programming the DOUTLATCH register,
Bit D1 to 1 sets the output latches transparent. The data outputs
can also be disabled (three-stated) by setting the DOUTDISABLE
Register 0x01, Bit D0 to 1.
The DCLK output can be used for external latching of the data
outputs. By default, the DCLK output tracks the value of the
DOUTPHASE register. By changing the DCLKMODE register,
the DCLK output can be held at a fixed phase, and the
DOUTPHASE register value is ignored.
To optimize the delay between the DCLK rising edge and the
data output transition, the DOUTDELAY register is used. By
default, there is approximately 8 ns of delay from the rising edge
of DCLK to the transition of the data outputs. See the High
Speed Timing Generation section for more information.
Switching the data outputs can couple noise into the analog
signal path. To minimize switching noise, set the DOUTPHASE
register to the same edge as the SHP sampling location, or up to
11 edges after the SHP sampling location. Other settings can
produce good results, but require experimentation. It is
recommended that the DOUTPHASE location not occur
between the SHD sampling location and 11 edges after the SHD
location. For example, if SHDLOC = 0, set DOUTPHASE to an
edge location of 12 or greater. If adjustable phase is not required
for the data outputs, the output latch can be left transparent
using Register 0x01, Bit D1.
Data output coding is normally straight binary, but can be
changed to gray coding by setting the GRAYEN Register 0x01,
Bit D2 to 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9925BBCZRL | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925 | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925BBCZ | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9927 | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZ | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。