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參數資料
| 型號： | AD9923ABBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 35/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923ABBCZRL |
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AD9923A
Rev. 0 | Page 35 of 88
XV1
XV2
XV13
HD
VSG
SECOND VPAT GROUP
START POSITION FOR SECOND VPAT GROUP
USES VSTARTSECOND REGISTER
0
Figure 47. Example of Second VPAT Group During Sensor Gate Line
VD
XV1 TO XV13
HD
REGION 1: SWEEP REGION
LINE 0
LINE 1
REGION 0
REGION 2
LINE 24
LINE 25
LINE 2
SCP 1
SCP 2
0
Figure 48. Example of Sweep Region for High Speed Vertical Shift
Figure 48 shows an example of sweep mode operation. The
number of required vertical pulses depends on the vertical
resolution of the CCD. The XV1 to XV13 output signals are
generated using the V-pattern registers (shown in Table 14).
A single pulse is created using the polarity and toggle position
registers. The number of repetitions is then programmed to
match the number of vertical shifts required by the CCD.
Repetitions are programmed in the V-sequence registers using
the VREP registers. This produces a pulse train of the appropriate
length. Normally, the pulse train is truncated at the end of the
HD line length, but with sweep mode enabled, the HD
boundaries are ignored. In Figure 48, the sweep region occupies
23 HD lines. After the sweep mode region is complete, normal
sequence operation resumes in the next region. When using
sweep mode, set the region boundaries, using the sequence
change position registers, to the appropriate lines to prevent the
sweep operation from overlapping with the next V-sequence.
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
can be configured into a multiplier region. This mode uses the
V-pattern registers in a slightly different manner. Multiplier mode
can be used to support unusual CCD timing requirements, such
as vertical pulses that are wider than the 13-bit V-pattern toggle
position counter.
The start polarity and toggle positions are used in the same
manner as the standard VPAT group programming, but the
VLEN register is used differently. Instead of using the pixel
counter (HD counter) to specify the toggle position locations
(XVTOG1, XVTOG2, XVTOG3, XVTOG4, XVTOG5, and
XVTOG6) of the VPAT group, the VLEN value is multiplied by
the XVTOG value to allow very long pulses to be generated. To
calculate the exact toggle position, counted in pixels after the
start position, use the following equation:
Multiplier Mode Toggle Position
=
XVTOG
×
VLEN
Because the XVTOG value is multiplied by the VLEN value, the
resolution of the toggle position placement is reduced.
If VLEN = 4, the toggle position accuracy is reduced to four
pixel steps, instead of single pixel steps. Table 18 summarizes
how the VPAT group registers are used in multiplier mode
operation. In multiplier mode, the VREP registers should be
programmed to the value of the highest toggle position.
The example shown in Figure 49 illustrates this operation. The
first toggle position is 2, and the second toggle position is 9. In
nonmultiplier mode, this causes the V-sequence to toggle at
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| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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