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參數資料
| 型號： | AD9923ABBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 61/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923ABBCZRL |
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AD9923A
STANDBY MODE OPERATION
The AD9923A contains three standby modes to optimize the
overall power dissipation in various applications. Bits[1:0] of
Register 0x00 control the power-down state of the device:
Rev. 0 | Page 61 of 88
STANDBY[1:0] = 00 = normal operation (full power)
STANDBY[1:0] = 01 = Standby 1 mode
STANDBY[1:0] = 2 = Standby 2 mode
STANDBY[1:0] = 3 = Standby 3 mode (lowest power)
Table 42 and Table 43 summarize the operation of each power-
down mode. Note that when OUTCONTROL = LO, it takes
priority over the Standby 1 and Standby 2 modes in determining
the digital output states, but Standby 3 mode takes priority over
OUTCONTROL. Standby 3 has the lowest power consumption,
and can shut down the crystal oscillator circuit between CLI
and CLO. If CLI and CLO are being used with a crystal to
generate the master clock, this circuit is powered down and
there is no clock signal. When returning the device from
Standby 3 mode to normal operation, reset the timing core at
least 500 μs after writing to the STANDBY register (Bits[1:0],
Address 0x00). This allows sufficient time for the crystal circuit
to settle. The vertical and shutter outputs can be programmed
to hold a specific value during the Standby 3 mode using
Register 0xE2, as detailed in Table 43. The vertical outputs can be
programmed to hold a specific value when OUTCONTROL =
low, or when in Standby 1 or Standby 2 mode, by using
Register 0xF3. The following list provides guidelines for the
mapping of the bits in these registers to the various vertical and
shutter outputs when the device is in one of the three standby
modes, or when OUTCONTROL = low.
Standby 3 mode takes priority over OUTCONTROL for
determining the output polarities.
These polarities assume OUTCONTROL = high, because
OUTCONTROL = low takes priority over Standby 1 and
Standby 2.
Standby 1 and Standby 2 set H and RG drive strength to
their minimum values (4.3 mA).
VD and HD default to High-Z status when in slave mode
regardless of standby mode or OUTCONTROL status.
This feature is useful during power-up if different polarities are
required by the V-driver and CCD to prevent damage.
It is important to note that when VDR_EN = 0 V, V1 to V13 are
at VM, and SUBCK is at VLL regardless of the state of the value
of the STANDBY and OUTCONTROL registers.
Table 42. Standby Mode Operation
I/O Block
AFE
Timing Core
CLO Oscillator
CLO
HL
H1
H2
H3
H4
RG
VD
5
HD
DCLK
D0 to D11
1
To exit Standby 3, write 00 to STANDBY (Bits[1:0], Address 0x00), then reset the timing core after 500 μs to guarantee proper settling of the oscillator.
2
Standby 3 mode takes priority over OUTCONTROL for determining the output polarities.
3
These polarities assume OUTCONTROL = high, because OUTCONTROL = low takes priority over Standby 1 and Standby 2.
4
Standby 1 and Standby 2 set H and RG drive strength to their minimum values (4.3 mA).
5
VD and HD default to High-Z status when in slave mode regardless of Standby mode or OUTCONTROL status.
Standby 3 (Default)
1
,
2
Off
Off
Off
High
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Low
Low
Low
Low
OUTCONTROL = LOW
2
No change
No change
No change
Running
Low
Low
High
Low
High
Low
VDHDPOL value
VDHDPOL value
Running
Low
Standby 2
3
,
4
Off
Off
On
Running
Low (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
VDHDPOL value
VDHDPOL value
Low
Low
Standby 1
3
,
4
Only REFT, REFB on
On
On
Running
Low (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Running
Running
Running
Low
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