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參數(shù)資料
型號: AD9923ABBCZRL
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA105
封裝: 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105
文件頁數(shù): 78/88頁
文件大小: 852K
代理商: AD9923ABBCZRL
AD9923A
Table 52. Memory Configuration Registers
Address
(Hex)
Bits
Value
90
[4:0]
0
91
[4:0]
0
Rev. 0 | Page 78 of 88
Data
Default
Update Name
VD
VD
Description
Total number of V-pattern groups.
Total number of V-sequences.
VPAT_NUM
VSEQ_NUM
Table 53. Standby Polarity, Shutter Mux, and FG_TRIG Registers
Address
(Hex)
Bits
Value
Update Name
E2
[24:0]
0
SCK
Data
Default
Description
Programmable polarities for vertical and shutter outputs during Standby 3.
[0] = XV1 polarity.
[1] = XV2 polarity.
[2] = XV3 polarity.
[3] = XV4 polarity.
[4] = XV5 polarity.
[5] = XV6 polarity.
[6] = XV7 polarity.
[7] = XV8 polarity.
[8] = XV9 polarity.
[9] = XV10 polarity.
[10] = XV11 polarity.
[11] = XV12 polarity.
[12] = XV13 polarity.
[13] = VSG1 polarity.
[14] = VSG2 polarity.
[15] = VSG3 polarity.
[16] = VSG4 polarity.
[17] = VSG5 polarity.
[18] = VSG6 polarity.
[19] = VSG7 polarity.
[20] = VSG8 polarity.
[21] = XSUBCK polarity.
[22] = VSUB polarity.
Note: controls polarity for Standby 1, Standby 2, Standby 3, or if
OUTCONTROL = low.
[23] = MSHUT polarity.
Note: controls polarity for Standby 1, Standby 2, Standby 3, or if
OUTCONTROL = low.
[24] = STROBE polarity.
Note: controls polarity for Standby 1, Standby 2, Standby 3, or if
OUTCONTROL = low.
0: counters behave the same as AD9923 in sweep region.
1: enables additional toggles after last repeat of sweep region.
Required start-up register; must be set to 0x60
Test register.
0: use VSUB0, 1: Use SHUT0 ^ VSUB0.
0: use VSUB1, 1: Use SHUT0 ^ VSUB1.
Test register. Set to 0.
0: use SHUT0 ^ SHUT1.
1: Use SHUT0 ^ SHUT2.
FG_TRIG operation enable and field count selection.
[2:0] Selects field count for pulse (based on mode field counter).
[3] = 1 to enable FG_TRIG signal output.
STANDBY3POL
E6
EA
EB
F1
[0]
[9:0]
[11:0]
[12]
[13]
[14]
[15]
[3:0]
0
0
300
0
0
0
0
0
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
VCNT_RUN
TEST3
TEST4
VSUB0_MUX
VSUB1_MUX
TEST5
SHUT1_SHUT2_MUX
FG_TRIGEN
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