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參數(shù)資料
型號(hào)： AD9923ABBCZRL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA105
封裝： 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105
文件頁(yè)數(shù)： 49/88頁(yè)
文件大?。?/td> 852K
代理商： AD9923ABBCZRL
AD9923A
Rev. 0 | Page 49 of 88
Table 38. SUBCK and TRIGGER Register Parameters
Length
(Bits)
TRIGGER
8
READOUTNUM
3
EXPOSURENUM
12
Register
Range
On/off for eight signals
0 to 7 fields
0 to 4095 fields
Description
0: triggers SHUT0 signal.
1: triggers SHUT1 signal.
2: triggers SHUT2 signal.
3: triggers SHUT3 signal.
4: triggers VSUB0 signal.
5: triggers VSUB1 signal.
6: triggers EXPOSURE operation.
7: triggers READOUT operation.
Number of fields to suppress SUBCK after exposure.
Number of fields to suppress to SUBCK and VSG during exposure time (low
speed shutter).
Disable VD/HD output during exposure.
1 = disable VD.
0 = enable VD.
SUBCK start polarity for SUBCK1 and SUBCK2.
First toggle positions for first SUBCK pulse (normal shutter).
Second toggle positions for first SUBCK pulse (normal shutter).
First toggle positions for second SUBCK pulse in last line (high precision).
Second toggle positions for second SUBCK pulse in last line (high precision).
Total number of SUBCKs per field, at one pulse per line.
Number of pulses, after the VSG line, to suppress SUBCK.
Additional masking of SUBCK output.
0 = no additional mask.
1 = start mask at VD edge.
2 = use internal SHUT3 signal to mask.
VDHDOFF
SUBCKPOL
1
SUBCK1TOG1
1
SUBCK1TOG2
1
SUBCK2TOG1
1
SUBCK2TOG2
1
SUBCKNUM
1
SUBCKSUPPRESS
1
12
SUBCKMASK
1
1
Register is not VD updated, but updated at the start of the line after the sensor gate line.
Shutter Outputs
The AD9923A contains three shutter output pins: VSUB,
MSHUT, and STROBE. Internally, there are six possible shutter
signals available: VSUB0, VSUB1, SHUT0, SHUT1, SHUT2,
and SHUT3. Any of these signals, and the following combinations:
SHUT0 ^ VSUB0, SHUT0 ^ VSUB1, SHUT0 ^ SHUT1,
SHUT0 ^ SHUT2, can be mapped to any of the output pins
using the VSUB_CTRL, MSHUT_CTRL, and STROBE_CTRL
registers.
1
1
12
12
12
12
12
On/off
High/low
0 to 4095 pixel locations
0 to 4095 pixel locations
0 to 4095 pixel locations
0 to 4095 pixel locations
1 to 4095 pulses
0 to 4095 pulses
0 to 3 masking mode
2
The VSUB signals behave differently than the SHUT signals,
and are generally used for the VSUB output pin. If a more generic
approach is desired for the shutter signals, the SHUT signals can
be used for the VSUB output pin.
It is also possible to configure the SYNC pin as an output and
send one of the internal shutter signals, or the combinations listed
above, to the SYNC pin using the TESTO_CTRL register
function. This provides the flexibility of outputting up to four
shutter outputs if the external SYNC input function is not needed.
VSUB Signal Operation
The CCD readout bias (VSUB) can be programmed to accom-
modate different CCDs. Figure 67 shows two available modes.
In Mode 0, VSUB goes active when the exposure begins during
the field of the last SUBCK. The on position (rising edge in
Figure 67) is programmable to any line within the field. VSUB
remains active until the end of the image readout. In Mode 1,
the VSUB is not activated until the start of the readout.
A function called VSUB_KEEPON is also available. When the
appropriate VSUB_KEEPON bit is set high, the VSUB output
remains active, even after the readout has finished. To disable
the VSUB at a later time, return this bit to low.
The AD9923A contains two programmable VSUB signals,
VSUB0 and VSUB1. Either of these signals can be mapped to
the VSUB output pin, the MSHUT pin, or the STROBE pin.
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