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參數資料
| 型號： | AD9923ABBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 18/88頁 |
| 文件大?。?/td> | 852K |
| 代理商： | AD9923ABBCZRL |
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AD9923A
HORIZONTAL CLAMPING AND BLANKING
The AD9923A horizontal clamping and blanking pulses are
fully programmable to suit a variety of applications. Individual
controls are provided for CLPOB, PBLK, and HBLK during
different regions of each field. This allows dark pixel clamping
and blanking patterns to be changed at each stage of the readout
to accommodate different image transfer timing and high speed
line shifts.
Rev. 0 | Page 18 of 88
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 23. These two signals are independently
programmed using the registers in Table 11. SPOL is the start
polarity for the signal, and TOG1 and TOG2 are the first and
second toggle positions of the pulse. Both signals are active low
and should be programmed accordingly.
A separate pattern for CLPOB and PBLK can be programmed
for each V-sequence. As described in the Vertical Timing
Generation section, several V-sequences can be created, each
containing a unique pulse pattern for CLPOB and PBLK.
Figure 46 shows how the sequence change positions divide the
readout field into regions. A different V-sequence can be
assigned to each region, allowing the CLPOB and PBLK signals
to change with each change in the vertical timing. Unused CLPOB
and PBLK toggle positions should be set to 8191.
CLPOB and PBLK Masking Area
The AD9923A allows the CLPOB and/or PBLK signals to be
disabled during certain lines in the field without changing the
existing CLPOB and/or PBLK pattern settings.
To use CLPOB masking, the CLPMASKSTART and CLPMASKEND
registers are programmed to specify the starting and ending lines
in the field where the CLPOB patterns are ignored. There are three
sets of CLPMASKSTART and CLPMASKEND registers,
allowing up to three CLPOB masking areas to be created.
CLPOB masking registers are not specific to a given V-sequence;
they are active for any existing field of timing. To disable the
CLPOB masking feature, set these registers to the maximum
value, 0xFFF (default value).
To use PBLK masking, the PBLKMASKSTART and
PBLKMASKEND registers are programmed to specify the
starting and ending lines in the field where the PBLK patterns
are ignored. There are three sets of PBLKMASKSTART and
PBLKMASKEND registers, allowing the creation of up to three
PBLK masking areas.
PBLK masking registers are not specific to a given V-sequence;
they are active for any existing field of timing. To disable the
PBLK masking feature, set these registers to the maximum
value, 0xFFF (default value).
Table 11. CLPOB and PBLK Pattern Registers
Register
Length (Bits)
CLPOBPOL
1
PBLKPOL
1
CLPOBTOG1
13
CLPOBTOG2
13
PBLKTOG1
13
PBLKBTOG2
13
CLPMASKSTART
12
CLPMASKEND
12
PBLKMASKSTART 12
PBLKMASKEND
12
Range
High/low
High/low
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 4095 line location
0 to 4095 line location
0 to 4095 line location
0 to 4095 line location
Description
Starting polarity of CLPOB for each V-sequence
Starting polarity of PBLK for each V-sequence
First CLPOB toggle position within the line for each V-sequence
Second CLPOB toggle position within the line for each V-sequence
First PBLK toggle position within the line for each V-sequence
Second PBLK toggle position within the line for each V-sequence
CLPOB masking area—starting line within the field (maximum of three areas)
CLPOB masking area—ending line within the field (maximum of three areas)
PBLK masking area—starting line within the field (maximum of three areas)
PBLK masking area—ending line within the field (maximum of three areas)
3
2
1
HD
CLPOB
PBLK
PROGRAMMABLE SETTINGS:
1
START POLARITY (CLAMP AND BLANK REGIONS ARE ACTIVE LOW).
2
FIRST TOGGLE POSITION.
3
SECOND TOGGLE POSITION.
ACTIVE
ACTIVE
0
Figure 23. Clamp and Preblank Pulse Placement
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相關代理商/技術參數 |
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| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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