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參數資料
| 型號： | AD9923ABBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 6/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923ABBCZRL |
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AD9923A
Parameter
BLACK LEVEL CLAMP
Clamp Level Resolution
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 1023)
ANALOG-TO-DIGITAL CONVERTER (ADC)
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code 15)
Maximum Gain (VGA Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
1
Input signal characteristics are defined as shown in Figure 3.
Rev. 0 | Page 6 of 88
Conditions/Comments
Measured at ADC output
Includes entire signal chain
Default CDS gain (0 dB)
12 dB gain applied
AC-grounded input, 6 dB gain applied
Measured with step change on supply
Min
12
1.0
6.0
42.0
Typ
1024
0
255
±0.5
Guaranteed
2.0
2.0
1.0
6.5
42.5
0.1
1.0
50
Max
+1.0
7.0
43.0
Unit
Steps
LSB
LSB
Bits
LSB
V
V
V
dB
dB
%
LSB rms
dB
200mV MAX
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V MAX
INPUT SIGNAL RANGE
(0dB CDS GAIN)
0
Figure 3. Signal Characteristics
TIMING SPECIFICATIONS
C
L
= 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f
CLI
= 36 MHz, unless otherwise noted.
Table 6.
Parameter
MASTER CLOCK, CLI
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal Pixel Position 0
AFE CLPOB Pulse Width
1, 2
Allowable Region for HD Falling Edge to CLI Rising Edge
SHP Inhibit Region
AFE SAMPLE LOCATION
1
SHP Sample Edge to SHD Sample Edge
DATA OUTPUTS
Output Delay from DCLK Rising Edge
1
Inhibited Area for DOUTPHASE Edge Location
Pipeline Delay from SHP/SHD Sampling to Data Output
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
1
Parameter is programmable.
2
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Conditions/Comments
Only valid in slave mode
Only valid in slave mode
Symbol
t
CONV
t
CLIDLY
t
HDCLI
t
SHPINH
t
S1
t
OD
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
DV
Min
27.8
11.2
2
4
30
11.6
SHD
16
36
10
10
10
10
10
Typ
13.9
6
20
13.9
8
Max
16.6
t
CONV
2
39
SHD + 11
Unit
ns
ns
ns
Pixels
ns
Edge location
ns
ns
Edge location
Cycles
MHz
ns
ns
ns
ns
ns
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相關代理商/技術參數 |
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| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
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