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參數(shù)資料
型號(hào)： AD9923ABBCZRL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA105
封裝： 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105
文件頁(yè)數(shù)： 71/88頁(yè)
文件大小： 852K
代理商： AD9923ABBCZRL
AD9923A
Rev. 0 | Page 71 of 88
Table 46. Miscellaneous Registers
Address
(Hex)
Bits
10
[0]
11
[0]
12
[0]
Data
Default
Value
0
0
1
Update
Type
SCK
VD
SCK
Name
SW_RST
OUTCONTROL
SYNCENABLE
Description
Software reset. Bit resets to 0.
1: reset Register 0x00 to Register 0x91 to default values.
0: make all outputs dc inactive.
1: enable outputs at next VD edge.
0: configure Ball G7 as an output signal, determined by
Register 0x12, Bits[9:8].
1: external synchronization enable (configure Ball G7 as SYNC input).
Test mode only. Must be set to 0.
When SYNCENABLE = 0, selects which signal is output on the SYNC pin.
0: CLPOB.
1: PBLK.
2: GPO (from Register 0x1A).
3: TESTOUT (from shutter registers).
SYNC active polarity.
0: active low.
1: active high.
Suspends clocks during SYNC active pulse.
0: don’t suspend.
1: suspend.
Timing core reset bar.
0: reset TG core.
1: resume operation.
CLO oscillator reset.
0: oscillator in power-down state.
1: resume oscillator operation.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Serial update line. Sets the HD line within the field to update the VD
updated registers.
Prevents the updating of the VD updated registers.
0: normal update.
1: prevent update of VD updated registers.
General-purpose output (GPO) value when SYNCENABLE = 0 and
OUTPUTPBLK = 2.
0: GPO is low at next VD edge.
1: GPO is high at next VD edge.
13
14
15
16
17
18
[7:1]
[9:8]
[0]
[0]
[0]
[0]
[7:0]
[8]
[11:0]
0
0
0
0
0
0
0
0
0
SCK
SCK
SCK
SCK
SCK
VD
TEST
OUTPUTPBLK
SYNCPOL
SYNCSUSPEND
TGCORE_RSTB
OSC_RST
TEST1
TEST2
UPDATE
19
1A
[0]
[0]
0
0
SCK
VD
PREVENTUP
GPO
Table 47. VD/HD Registers
Address
(Hex)
Bits
20
[0]
21
[0]
22
[12:0]
[24:13]
Data
Default
Value
0
0
0
0
Update
Type
SCK
SCK
VD
Name
MASTER
VDHDPOL
HDRISE
VDRISE
Description
VD/HD master or slave mode.
0: slave mode.
1: master mode.
VD/HD active polarity.
0: low.
1: high.
Rising edge location for HD.
Rising edge location for VD.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9923BBCZ 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:
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