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| 型號： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料 |
| 文件頁數： | 11/92頁 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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Agere Systems Inc.
19
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Automatic Test Pattern Generation (ATPG), Scan Sequence Modification (SSM),
and Signature Analysis (continued)
Hardware Generation of Test Sequences (continued)
The complementary sequences are created by enabling ATPG with BSM2 output inversion also enabled (see
under the heading TDO Inversion).
Throughout this section,
N stands for the number of nets tested by means of a selected/attached B-S chain.
Walking Sequence ATPG
The walking-one (zero) sequence has special significance for interconnect test and is also useful for other pur-
poses. Given
N nets, the algorithm generates an N x N matrix with the diagonal of 1 (0). All other elements of the
matrix are 0 (1). The hardware to generate this sequence is shown in Figure 3. It consists of two downcounters, NC
(which is loaded via NCR) and LPC. Both NCR and LPC must be initialized to
N by the user. After NC downcounts
to zero, it is reloaded with the contents of NCR, and LPC is decremented. (SDR, as always, contains the length of
the selected/attached B-S path.) NC and LPC are input to a comparator that outputs a 1 only when the two
counters are equal. The sequence of bits produced from this output is the serialized test pattern.
The operation is as follows: The controlling processor initializes both NCR (and implicitly NC) and LPC to
N. Since
initially NC = LPC, a 1 is output and this is the first bit output from the test generator. After that, each time the ATPG
is enabled by the SSM, the NC is decremented and the comparator output is shifted out as a bit of the test vector.
After the test vector is generated (identified by SDC = NC = 0), LPC is decremented to
N – 1, and NC is reinitialized
to
N by NCR. The operation repeats, except that now a 1 is output when NC = N – 1. This operation repeats until
both counters are zero. This algorithm will generate
N patterns, each of length N and the ith pattern has a 1 in loca-
tion i, and 0 in all other locations. The SSM ensures that the test vector bits are correctly positioned in each serial
test vector. This is the walking-one sequence. Note that the complementary sequence, walking zeros, can be trivi-
ally constructed by complementing the output.
5-6312 (F)
Figure 3. Walking Sequence Test Generator
NET COUNT REGISTER (NCR)
NET COUNTER (NC)
=
LOOP COUNTER (LPC)
COMPARATOR
WALKING SEQUENCE
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