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| 型號(hào)： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料 |
| 文件頁數(shù)： | 15/92頁 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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22
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
BIST—Self-Test of the BSM2
Introduction
Definition and Classification of BIST in the BSM2
BIST for the BSM2 device must be clearly distin-
guished from system- or board-level BIST that can be
carried out (e.g., using ATPG) or initiated through a B-S
chain (e.g., by scanning a RUNBIST instruction into a
device on a B-S chain) using the capabilities of the
BSM2.
Since the BSM2 is designed to enhance board and
system testability, it follows that the quality of the BSM2
itself must be very high. As in the previous design
(497AA), both the memories (here the TVO and TVI
FIFOs) and the random logic are designed to include
Agere state-of-the-art BIST.
Memory BIST ensures 100% fault coverage over an
extended fault model (well beyond the stuck-at fault
model). The patented methodology used involves auto-
matic insertion of BIST in regular structures. This BIST
combines the characteristics of low overhead and com-
plete absence of BIST signature aliasing (i.e., pres-
ence of a modeled fault will always cause a test
failure).
The core portions of the random logic include partial-
scan BIST (PSBIST) techniques giving 96% stuck-at
fault coverage. Moreover, non-BIST scan techniques
are used to raise fault coverage for manufacturing test.
All latches, flip-flops, etc. in the noncore logic are
included in two full-scan paths used in manufacturing
test.
95% of the circuitry in the BSM2 contains BIST fea-
tures used in manufacturing test that can also be
invoked by a controlling processor when the BSM2 is
an assembled component in a board or system. The
remaining 5% comprises sections of the processor
interface and the CBIST register. Failure in either of
these parts of the BSM2 can be rapidly detected by
application software.
This section addresses the hardware self-test features
built into the BSM2.
Three of the BSM2 self-test algorithms can be
accessed by the user when the BSM2 is embedded in
product. These algorithms are the memory self test, the
random logic self-test, and memory retention tests. The
last type is beyond the scope of this manual, and users
desiring further information about it should contact
Agere.
Impact on Connected Devices
When random logic BIST is activated in the BSM2, all
of the TAP outputs and the USEROUTx signals are dis-
abled (3-stated). This is not necessary (and not done)
during memory BIST.
Memory BIST in the BSM2
Following memory BIST, memory in the BSM2 will have
been corrupted; however, address pointers, etc. will
retain their original values.
Random Logic BIST in the BSM2
Random logic BIST tests only the core combinational
and registered logic of the design. Some of the periph-
eral I/O logic for communicating with the controlling
processor operates in normal (nontest) mode through-
out random logic BIST in order to allow communication
of BIST status, etc.
When random logic BIST is running, the only register of
the BSM2 that can be accessed by the controlling pro-
cessor is the CBIST register. The other registers are
locked and not unlocked until random logic BIST ends.
Random logic BIST o” is defined by the XECBIST bit
having the value 1 and the RLSKP bit’s having the
value 0. Random logic BIST off is defined by the
XECBIST bit’s having the value 0 or the RLSKP bit’s
having the value 1. Random logic BIST must be off in
order read the correct result signature.
BUG (August, 1988): The RDY signal is disabled (3-
stated) during random logic BIST and is not available
for use in handshake with the controlling processor.
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