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參數(shù)資料
型號: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料
文件頁數(shù): 33/92頁
文件大小: 1041K
代理商: 1215E
Agere Systems Inc.
39
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix B—BSM2 Register Descriptions (continued)
CSC: Control-Scan/Clock Register (continued)
SCT[2:0]
(Scan Type Bits)—These three bits encode the name of a TAP Controller state. The state designated
by SCT[2:0] is the one in which shifting via TDI/TDO will occur during a scan operation. (See The
BSM2 Scan Process.)
Note:
These bits must be set for Shift-DR scan type (010) for ATPG operation.
DET[1:0]
(Destination Type Bits)—These two bits encode the name of a TAP Controller state. The state desig-
nated by DET[1:0] is the stable state in which the current or next scan operation will terminate. The
BSM2 takes advantage of the fact that TAP Controllers of a selected/attached B-S chain can remain
indefinitely in stable states with the clock signal on the TCK pin of a TAP running. (See The BSM2
and Signature Analysis.) These bits determine the terminal state of a scan operation whether or not
ATPG is employed.
Note:
These bits must be set for either the Test-Logic-Reset or Run-Test/Idle destination TAP controller
states (i.e., set to 00 or 01) for ATPG operation.
RTD[3:0]
(Retimed Delay Control Bits)—Values written to these bits provide control of the BSM2 retimed delay
control for electrically distant B-S chains. According to the decimal value of the four bits, RTD[3:0]
provides for from 0 to 11 cycles of TCK delay as described in the section on Retimed Delay Support.
LP
(Low Power Mode Bit)—A 0 in this bit causes the BSM2 to place itself in its normal operational mode.
In this mode, its TCK divider registers are enabled even when the part is otherwise idle. A 1 in this bit
causes the BSM2 to place itself in low power mode with its TCK divider registers disabled (off).
Designated Scan Type
SCT2 SCT1 SCT0
Shift-IR
0
Pause-IR
0
1
Shift-DR
0
1
0
Pause-DR
0
1
Test-Logic-Reset
1
X
0
Run-Test/Idle
1
X
1
Destination TAP Controller State
DET1
DET0
Test-Logic-Reset
0
Run-Test/Idle
0
1
Pause-IR
1
0
Pause-DR
1
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