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參數資料
型號: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料
文件頁數: 66/92頁
文件大小: 1041K
代理商: 1215E
Agere Systems Inc.
69
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix C—BSM2 (497AE) Data Sheet (continued)
Read/Write Cycle Timing—Synchronous Operation
During a read or write operation, if RA = 0, then the PTR (pointer register) is addressed; otherwise, the internal reg-
ister pointed to by the PTR is selected.
A read cycle starts when the BSM2 is enabled and R/W* = 1. The D[7:0] output buffers are enabled during a read
cycle. Also, the D[7:0] outputs become valid on the first rising edge of TCKIN after DAV* goes to logic 0. The read
cycle terminates when the BSM2 has detected a logic 1 at DAV* on a subsequent TCKIN rising edge. This implies
that every read cycle consumes at least two TCKIN cycles (see Figure 7).
D[7:0] output buffers are controlled asynchronously by CE* and R/W*. When a BSM2 register is to be read after a
series of writes, D[7:0] change from inputs to outputs; this takes a maximum of 15 ns.
Note:
R/W* should be stable before or at the same time as CE* goes to logic 0. Otherwise, there is the potential
for bus conflict (see Figure 7).
5-6319 (F)
Notes:
1. D[7:0] output buffers are turned on after CE* goes to logic 0; DAV* going to logic 0 while R/W* = 1 initiates the read cycle.
2. Valid data are placed on the data bus by the BSM2 after the rising edge of TCKIN.
3. D[7:0] output buffers are disabled after CE* goes to logic 1.
4. DAV* = 1 at the rising edge of TCKIN causes the BSM2 to terminate the read cycle.
5. No further read operations will occur (i.e., no new data will be read from the BSM2) while DAV* = 0.
Figure 7. 497AE Read Cycle Timing Diagram
RA
R/W*
DAV*
3
2
3
2
14
15
5
4
EXTENDED CYCLE
SHORT CYCLE
TCKIN
CE*
D[7:0]
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相關代理商/技術參數
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1215-EN 制造商:Thomas & Betts 功能描述:INSERT BUSHING--2
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