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| 型號： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料 |
| 文件頁數： | 7/92頁 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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Agere Systems Inc.
15
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Automatic Test Pattern Generation
(ATPG), Scan Sequence Modification,
and Signature Analysis
This section describes the BSM2 ATPG and scan
sequence modification (SSM). While the description
refers to interconnect test, this capability is general and
can be used to test logic through a selected/attached
B-S chain as well as device interconnection. It may
prove useful for cluster test—testing of non-B-S
devices via the B-S paths of devices that surround the
non-B-S devices. It can also be used to test the internal
logic of devices.
In carrying out interconnect testing, it is possible that
bus conflicts could arise if multiple devices on a single
bus were enabled simultaneously. The BSM2 avoids
this situation by using a concise form of a wiring list to
inform the ATPG function of which B-S cells are at
device inputs, which are at outputs, and which must be
held to a constant value (e.g., because they drive
enable signals on other devices). (See the section titled
This section initially describes some of the BSM2 regis-
ters and memory blocks that are used for ATPG. The
operation of the SSM, the subsystem that modifies the
scan vectors and controls the response compression,
is then described in detail. The hardware implementa-
tion of the test sequences in the ATPG mode is illus-
trated.
BSM2 Registers Related to ATPG
In this section, the registers used during ATPG are
reviewed. Under the heading “Appendix B—BSM2
Internal Register Descriptions,” all registers are
described in greater detail.
Control of ATPG, SSM, and Signature Analysis
s
CUTI[09:08]—These bits, also called AMD[1:0], per-
mit the selection of one of the four possible patterns
that the BSM2 ATPG is capable of generating. The
output data of an ATPG algorithm may be inverted
prior to scanning into a selected/attached B-S scan
path under control of the AC bit (CUTI[03]) as illus-
trated in the description of the CUTI register.
s
The SSME bit (CUTI[04]) serves the function of
enabling or disabling SSM and, with it, the signature
analysis register (SAR).
ATPG-Related Registers
s
Loop counter (LPC)—This 16-bit counter contains
the number of serial tests that are to be applied to
the UUT. Every time a complete vector is shifted out,
this counter is decremented.
s
Scan duration register (SDR)—This 16-bit register
contains the length of each serial test vector to be
applied to the UUT. This value is the length of the
scan path—the total of the lengths of the B-S data
registers in all the chips on the selected/attached
B-S ring. The value from this register is loaded in a
scan duration counter (SDC) which is decremented
every time a vector bit is shifted out. When SDC
reaches zero, a signal is sent to decrement LPC.
Then, if LPC is not 0, the SDC is reloaded from the
SDR. When both SDC and LPC are zero, the BSM2
stops transmitting serial test data.
s
Net count register (NCR)—This 16-bit register is
used by the ATPG in conjunction with the net
counter (NC), to generate counting and walking
sequences.
s
tern generator (SAR and PRPG)—These are 32-bit
registers. The seed values for both of these registers
are programmable in advanced operational mode.
The PRPG is both readable and writable in the
advanced operational mode and write-only in the
497AA mode.
s
Control-Scan/Clock register (CSC)—In this register
the scan type bits (SCT[2:0]) must be set for Shift-
DR scan type (i.e., loaded with the pattern 010) for
ATPG operation. Also, the destination state for
ATPG should be set to either Test-Logic-Reset or
Run-Test/Idle. This is accomplished using the desti-
nation type bits (DET[1:0]).
s
IDLE counter register (IDLE)—This register should
be set to zero for ATPG operation to disable the IDT
bits of the CSC register.
The BSM2 has two 8K memory buffers, called the test
vector out (TVO) and test vector in (TVI) buffers. For
deterministic tests, these two buffers hold test vectors
and the response of the UUT. In the case of ATPG, the
SSM uses these to store a structure map of the scan
chain, as described in the next section.
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