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參數(shù)資料
型號: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料
文件頁數(shù): 79/92頁
文件大?。?/td> 1041K
代理商: 1215E
80
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix D—BSM2 (1215E) Data Sheet (continued)
Read/Write Cycle Timing—Asynchronous Operation
Read and write cycle operation in asynchronous mode is described by a series of figures in this section. The fig-
ures represent asynchronous operation of both the 497AE and the 1215E.
Notes:
1. CE* goes to logic 0. CE* is the main control signal for the device. All other signals are valid/meaningful only if this signal is active (= 0).
2. R/W* goes to logic 1. The R/W* and RA[4:0] signals can be set up before CE* becomes active. This diagram shows worst case access time
for each signal. If both signals are set up in advance of CE* becoming active, data becomes valid on D[15:0] at point 3 rather than
point 6.
3. When both CE* = 0 and R/W* = 1, the D[15:0] output buffers are turned on.
4. RDY becomes valid. The interval B represents the best case timing for RDY going to logic 1 after CE* becomes active. The worst case is
approximately 3 cycles of the signal on TCKIN after the previous CE* access.
5. Controlling processor drives valid address on RA[4:0].
6. Data becomes available on the data bus. The interval A is the access time of the device—time for address decoding and outputting data to
the data bus.
7. CE* going to logic 1 terminates the cycle. Although R/W* is shown as don’t care in this diagram, this signal should remain = 1 through this
point for normal read operations. Otherwise, a write operation could occur (see Figure 16). The situation depicted in the present figure illus-
trates that write may follow a read operation in one CE* cycle—if the proper write cycle timing is followed. In the 1215E device, multiple non-
memory reads can occur in a single CE* cycle by changing the address bus (RA[4:0]) and carefully maintaining proper data access time
from RA[4:0] to D[15:0] (interval A).
C. The interval C is the delay between RDY going to logic 1 and availability of data on the data bus in the case in which the device is not ready
when accessed—CE* is active, and the initial value of the signal on RDY is 0.
Figure 15. 1215E Read Cycle Timing Diagram
CE*
R/W*
RA[4:0]
D[15:0]
RDY
B
A
C
3
1
2
6
4
5
7
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