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| 型號： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料 |
| 文件頁數： | 14/92頁 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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Agere Systems Inc.
21
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Automatic Test Pattern Generation
(ATPG), Scan Sequence Modification
(SSM), and Signature Analysis (continued)
Hardware Generation of Test Sequences
(continued)
lines input to the multiplexor are selected as the test
output. This generates the set of
N-bit serial test vec-
tors comprising the serialized counting sequence. As
before, the complementary sequence can be con-
structed by inverting the output.
Pseudorandom ATPG
The third sequence that the SSM facilitates is the pseu-
dorandom sequence. This can be applied to the inter-
connect and the response compressed to a signature
to give a pass/fail indication. The techniques for design-
ing a pseudorandom test generator are well known and
are not described in this document. The BSM2 has a
32-bit PRPG, the seed of which can be programmed.
This generator can prove especially useful for cluster
test and for testing the internal logic of some devices
that do not have BIST.
Constant Output
Another useful mode of the ATPG is that in which a
constant 1 or constant 0 is shifted out via TDO. This
would be used when the BYPASS (all 1) or EXTEST
(all 0) instruction is being scanned into the IR of all the
devices in a selected/attached B-S chain.
Note:
While constant output ATPG is selected, the
SSM function must be disabled.
Programming ATPG and SSM Functions
The selection of the source of test vectors and the des-
tination of the test response is programmed in the CUTI
register, bits TIOM[2:0]. The ATPG type that is to be
selected is programmed in the configuration registers,
bits AMD[1:0]. Enabling/disabling of the SSM is also
controlled by the CUTI register, bit SSME. Finally, bit
AC in CUTI controls whether or not the output of the
ATPG is complemented. More details concerning these
registers are provided in Appendix B—BSM2 Internal
Register Descriptions.
The operation of the ATPG is synchronized with the
TAP State Tracker. When the TAP State Tracker indi-
cates that all the TAP controllers on the selected/
attached B-S chain have entered the Shift-DR TAP
controller state, and the TDO source has been set as
ATPG, the ATPG starts generating serialized algorith-
mic or pseudorandom test vectors. The response to
the test sequences generated by the ATPG is com-
pressed to a signature. The SAR is enabled only after
the first test vector is scanned out of the selected/
attached B-S chain. This is important in ensuring that
the unknown values that are scanned out when the first
vector is scanned in do not corrupt the signature. Also,
after the last ATPG vector is scanned in, another vec-
tor needs to be shifted in to scan out the last response.
This housekeeping is performed automatically in the
BSM2 and is transparent to the user. For the last vec-
tor, a constant value is scanned into the B-S chain to
allow access to the last response. In the BSM2, this
value is 1.
Low Power Mode
To minimize power dissipation from the BSM2 several
approaches can be taken.
CMOS power dissipation is strongly dependent on
input voltage levels. Maintaining logic levels within
0.5 V of VDD and VSS will minimize power dissipation in
any mode of operation.
The output loads, particularly the TAP signals, are a
large factor determining the power dissipation of the
device. 3-stating or disabling these signals when they
are not used will minimize power consumption.
To reduce power dissipation below 43 mW, four com-
plimentary approaches can be used when the device is
not executing a scan operation. To reduce power dissi-
pation to <5 mW, the external master clock for the
BSM2 should be disabled.
To achieve low (<43 mW) power dissipation,
s
All TAP output signals should be 3-stated. (This is
accomplished using the TOE* pin and the TOEB bit
in the 1215E and the TOEB bit alone in the 497AE.)
s
CE* should not become active.
s
No internal registers should change state.
s
TCK generator (clock divider) circuitry (the only inter-
nal registers changing state when the BSM2 is not
executing a scan operation) should be disabled by
setting the value of the CDIV[2] bit of the CSC regis-
ter to 1.
When these four actions have been taken, the power
dissipation of the BSM2 will be less than 43 mW. This
is mainly from the internal clock drivers switching the
capacitive load of the clock tree.
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