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| 型號： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料 |
| 文件頁數： | 77/92頁 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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Agere Systems Inc.
79
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix D—BSM2 (1215E) Data Sheet (continued)
Pin Descriptions (continued)
Table 17. 1215E Processor Interface Pins (continued)
The BSM2 interfaces with the board-level B-S ring, of which the BSM2 is master, through the five pins described in
the following table.
Table 18. 1215E Board-Level TAP Interface Pins
Table 19. 1215E Power and Ground Pins
Pin
Symbol
Name/Description
33, 31—30, 25,
22, 20—18,
40—39, 37—36,
34, 32, 29, 27
D[15:0]
Data Bus. These 16 pins are bidirectional, with D0 being the least significant
bit (LSB) and D15 the most significant bit (MSB). The data bus is active if the
device is enabled, and the direction of the data bus (input or output) is con-
trolled by the R/W* pin.
45
CE*
Chip Enable (Active-Low). This input pin is active-low. When CE* = 0, the
BSM2 is enabled or selected. The BSM2 data bus D[7:0] becomes active, and
the BSM2 internal registers can be accessed by the controlling processor.
47
R/W*
Read/Write Control (Active-Low). When the BSM2 is enabled (CE* = 0), this
input pin controls the direction of data transfer. When R/W* = 1, D[7:0] become
outputs, indicating a BSM2 internal register is to be read. When R/W* = 0,
D[7:0] become inputs, indicating a BSM2 internal register is to be written.
42—44, 46, 48
RA[4:0]
Address Bus. These five input pins drive the address bus of the 1215E. When
CE* = 0, the signals on these five lines define the register to be accessed for
the current operation.
Pin
Symbol
Name/Description
7TRST*
Test Reset (Active-Low). This output is a standard TAP test reset signal. When TRST* = 0,
the TAP controllers in any selected/attached B-S chain are asynchronously placed in their
Test-Logic-Reset TAP Controller state.
8TDI
Test Data Input. This is a standard TAP serial test data input pin with an internal pull-up
resistor. It receives serial test response from the local board B-S ring. All values arriving at
TDI are latched on the rising edge of TCKIN defined with respect to TCK. The test response
can be stored in an on-chip memory buffer or compressed into a 32-bit signature.
13
TCK
Test Clock. This is a 50% duty cycle, standard TAP test clock output pin. This programmable
clock output is derived from the TCKIN clock input. It is broadcast to all the B-S devices sup-
ported by the BSM2. Its maximum frequency is 65 MHz. Upon device reset, the default speed
of the signal on TCK is 1/128 of the speed of TCKIN.
16
TDO
Test Data Output. This is a 3-state, standard TAP serial test data output pin which drives the
local board B-S ring. All changes at TDO occur on the falling edge of TCK, referenced by
TCKIN. This pin can deliver prestored, deterministic test vectors, or algorithmic patterns gen-
erated by the ATPG (see Appendix A).
24
TMS
Test Mode Select. All changes at TMS occur on the falling edge of TCK, referenced by
TCKIN. Upon device reset, this pin outputs a constant value of 1.
Pin
Symbol
Name/Description
2, 17, 26, 38
PWR/VDD Power Supply. Four 3 Vdc power input pins are used to minimize potential noise
in the power supply.
5, 15, 21, 28,
35, 41
GND/VSS
Ground. Six ground pins (all at 0 Vdc) are used to minimize potential ground
bounces caused by high frequency and, potentially, high fanout pins such as TCK.
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