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| 型號： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料 |
| 文件頁數： | 76/92頁 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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78
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix D—BSM2 (1215E) Data Sheet (continued)
Pin Descriptions (continued)
The pins listed in Table 17 are used to provide the parallel interface between the BSM2 and a generic processor or
an ATE. An asterisk after a pin name indicates that that pin is active low.
Table 17. 1215E Processor Interface Pins
Pin
Symbol
Name/Description
1TOE*
TAP Output Enable. This active-low input is inverted and logically ORed with
the TDO Output Enable Control (TOEB) bit of the CUTO register. This pin pro-
vides the hardware mode of control of the 3-stating of TAP outputs. A detailed
explanation of operation is to be found in the description of the TOEB bit.
3TCKIN
Test Clock Input. This is a 50% duty cycle clock input with a maximum fre-
quency of 65 MHz. The TCK clock output is derived from this input clock. All
internal BSM2 operations are synchronous with respect to TCKIN.
4USERIN
User Input. This pin provides the capability of optionally monitoring the state of
a user selected signal without adding additional parallel I/O decoding logic to a
design. Because of pin limitations it is not available on the 497AE device. If it is
unused in the 1215E design, it should not be left floating, but tied either high or
low.
6
USEROUT0
User Output 0.This pin provides the means of signalling an interrupt to the
controlling processor according to certain conditions of the Test Data Memories
(FIFOs) (e.g., full, empty, etc.). The pin can be considered to be the output of a
9-input OR tree as follows: The USR0 bit in the CUTO register is ORed with the
STAT[15:12] and STAT [3:0] bits of the status register under control of a mask
programmed in the USRC0[7:0] bits of the CMU register.
9
USEROUT1
User Output 1. This pin provides the means of signalling an interrupt to the
controlling processor according to certain conditions of the Test Data Memories
(FIFOs) (e.g., full, empty, etc.). The pin can be considered to be the output of a
9-input OR tree as follows: The USR1 bit in the CUTI register is ORed with the
STAT[15:12] and STAT [3:0] bits of the status register under control of a mask
programmed in the USRC1[7:0] bits of the CMU register.
10
RST*
Reset (Active-Low). This active-low input pin can be used to synchronously
reset the entire device. A low pulse applied to RST* on the rising edge of the
signal on TCKIN is sufficient to initiate the BSM2 internal reset operation. All of
the output and bidirectional signals are set to a high-impedance state when
RST* = 0.
11, 12
SC[0:1]
(AMODE_SW,
ATEST_EN)
Scan Control. These pins are used for signals that run a scan-test of the
1215E. For normal operation, both signals should be tied to logic 1 or (because
they have internal pull-ups) left disconnected. For information on specific oper-
ation of the scan-test, contact Agere.
14
INT*
Interrupt (Active-Low). This is an active-low, open drain (open collector) out-
put pin. It generates processor interrupts (e.g., for FIFO over-/underflow or
completion of BIST). (See discussion under Interrupt Control. Compare to
USEROUT0 and USEROUT1, above.) For proper operation, this pin should be
terminated with a pull-up resistor.
23
RDY
READY. This is only used in asynchronous operation of the host interface. This
output pin provides the handshake signal to the controlling processor. The pin
has no function when the device is operating in 497AA compatible mode.
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