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參數(shù)資料
| 型號： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料 |
| 文件頁數(shù)： | 2/92頁 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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10
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Asynchronous and Synchronous
Interface Modes
Asynchronous Operation (497AE and 1215E)
The device pinout tables for the 497AE will be found in
Appendix C, beginning on page 67. The device pinout
tables for the 1215E will be found in Appendix D,
beginning on page 78.
An asterisk following a pin name indicates that it is
active-low.
In asynchronous interface mode, the CE* (chip enable)
pin is the main control signal. The R/W* pin controls the
direction of the data bus when CE* = 0.
On the output side of control, the RDY pin provides a
handshake from the BSM2 to the controlling processor.
The defining characteristic of asynchronous interface
mode is that the BSM2 protocol in this mode is inde-
pendent of the BSM2 master clock signal (TCKIN).
Internally, the device must synchronize with TCKIN;
therefore, the RDY signal may be required to indicate
whether BSM2 internal response to a previous access
by the controlling processor is complete.
The RDY signal will never be active unless CE* is.
An access cycle begins with the controlling processor
driving CE* = 0. The R/W* pin is driven to the logic
value defining the type of access desired.
If the BSM2 is not internally synchronized for a new
access, then the BSM2 will hold the RDY signal inac-
tive (=0) until internal synchronization is achieved.
When the RDY signal = 1, the controlling processor
can continue the access cycle.
At the end of the access cycle, the controlling proces-
sor drives CE* = 1. Any capture of data by the BSM2
occurs on the rising edge of the CE* signal—when CE*
goes inactive. In a read access cycle, any data on an
output bus of the BSM2 is only correct after RDY = 1.
The bus is no longer driven after the rising edge of
CE*.
Note:
If the BSM2 user can guarantee that accesses
by the controlling processor will be separated
by a minimum of 4 cycles on the TCKIN signal,
then RDY pin does not need to be monitored
by the controlling processor.
The Read sequence is as follows:
s
The controlling processor requests an access by
driving the signal on CE* low.
s
R/W* is driven high. Consequently, the data bus will
be driven by the BSM2 and contain data from the
selected register once RDY = 1.
s
After reading the data bus, the controlling processor
drives the signal on CE* high, terminating the access
cycle.
The Write sequence is as follows:
s
The controlling processor requests an access by
driving the signal on CE* low.
s
R/W* is driven low. Consequently, the data bus will
be driven by the controlling processor and contain
data to be written to a selected register.
s
The BSM2 drives the signal on RDY high.
s
The controlling processor drives the CE* signal high.
s
The data to be written is latched by the BSM2 on the
rising edge of the CE* signal.
s
Relevant timing diagrams for the 1215E begin with
on the pins with common names is identical to that of
the 1215E.
Synchronous Operation (497AE only)
Synchronous operation of the 497AE strongly resem-
bles the operation of the 497AA.
Relevant timing diagrams for the 497AE begin with Fig-
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