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參數資料
型號: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料
文件頁數: 36/92頁
文件大小: 1041K
代理商: 1215E
Agere Systems Inc.
41
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix B—BSM2 Register Descriptions (continued)
CUTI: Control-USEROUT1/Test Data/Interrupt Register
Purpose
Provides means by which an external processor may (a) control BSM2 internal connection, BSM2 ATPG algorithm
selection, and other means to effect output values on USEROUT1 and TDO and (b) enable/disable interrupts indi-
cating data overflow or underflow conditions, and (c) place the BSM2 in single step or TAP Manual Mode. Applica-
tion of elements of this register that control ATPG algorithm behavior is explained under the heading BSM2
Registers Related to ATPG. Applications related to scan sequence modification are explained under the heading
Scan-Sequence Modifier (SSM). Application to TDO signal value modification is explained under the heading TDO
Note:
CUTI[7:0] has the same function as in the TVMR register of the original BSM with the exception that
the TAP I/O Mode Bits (TIOM) now require three bits instead of two (as in the Test Resource Control
Bits of the 497AA).
Address (Octal)
01
Format
Default (Hex)
CUTI = 0000
Read-only Bits
None
Description
USR1
(USEROUT1 Control Bit)—The value of USR1 feeds the OR tree that drives USEROUT1 in the
1215E. When the value of the USR1 bit is 1, the BSM2 USEROUT1 pin will take the value of 1. When
the value of this bit is 0, the value of USEROUT1 pin is 0 unless one or more of the inputs to the OR
tree is driving the value 1. When USR1 is 0, the value of USEROUT1 may be interpreted as an inter-
rupt (active when equal to 1) accessible by a controller (e.g., a DMA controller) other than the control-
ling processor. The USR1 bit has no effect in the 497AE.
OUIM
(Data Over/Underflow Interrupt Mask Bit)—In order for the BSM2 to issue an interrupt—in order for
the INT* pin to be active—in the cases of over/underflow of the test data memories (FIFOs), this pin
must be set equal to 1. If this bit is set and either of the TVOM or TVIU bits of the status register = 1,
then the INT* pin will be active. See the description of the WDIM bit, below.
WDIM
(When Done Interrupt Mask Bit)—In order for the BSM2 to issue an interrupt—in order for the INT* pin
to be active—in the case of the DONE bit of status register being set, this bit must be set equal to 1. If
the value of this bit is 1, then an interrupt is enabled when the DONE bit is 1.
15
14
13
12—11
10
09—08
07—05
04
03 02
01—00
USR1 OUIM WDIM EXEC[1:0] MAN AMD[1:0] TIOM[2:0] SSME AC TC AINC[1:0]
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