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| 型號(hào)： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料 |
| 文件頁數(shù)： | 9/92頁 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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Agere Systems Inc.
17
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Automatic Test Pattern Generation (ATPG), Scan Sequence Modification (SSM),
and Signature Analysis (continued)
Scan-Sequence Modifier (SSM) (continued)
A test algorithm or test generator generates type 1 data. The generated data is a function of the test algorithm and
number of nets, and is independent of the type of nets, their ordering, etc. Type 2 and type 3 data is typically pro-
vided by test generation software that format the test sequences. It is the critical necessity of type 2 and type 3
data that makes it difficult to automatically generate interconnect test sequences in a board- or system-level BIST
environment. The technique that the BSM2 uses takes advantage of the fact that type 2 and type 3 data are static.
Consequently, if the value of this data and its location is recorded once, then it can be easily inserted into the out-
put scan sequence, and used for identifying the cells with useful test information that should be compressed by the
signature analysis register (SAR).
SSM-ATPG Mode
Figure 2 shows the SSM configuration with ATPG as the TDO source and SAR as the TDI destination. To achieve
this configuration SSM is enabled by setting the SSME bit.
Assume there are
L scan cells on the currently selected/attached B-S chain. The type 2 (control) data are placed in
two buffers, occupying
L bits of each buffer. The TVO/TVI memories (each 8K) of the BSM2 serve as the buffers.
There is a one-to-one mapping between the
L locations of these buffers and the L scan cells on the selected/
attached B-S chain. The controlling processor initializes TVI and TVO with type 2 data derived from UUT structural
information. TVI identifies the control cells while TVO identifies input/output cells and supplies the data for control
cells.
A 1 in location
n in TVI identifies a control cell at position n in the selected/attached B-S chain. The value in TVO at
the same location (
n) contains the logic value that must be shifted into that control cell to avoid conflict during test-
ing.
A 0 in location
m in TVI implies that the cell in position m of the selected/attached B-S chain is either an input cell
or output cell during the given test. A 1 in location
m in TVO identifies the cell as an output cell and ATPG is
enabled to supply test data for that cell location. A 0 in location
m in TVI combined with a 0 in location m in TVO
identifies the corresponding cell of the selected/attached B-S chain as an input cell. Since the data for such a cell is
type 3, or filler data, any value can be applied to the scan cell at the corresponding B-S chain location. The BSM2
will always generate a 0 for filler data.
The table below defines the operation of the SSM and its interaction with SAR and the test pattern generator in the
ATPG mode.
Table 1. ATPG Mode with SSM Enabled: How ith Bits of TVI and TVO Encode Cell Type and Control Source
of TDO and Actions of ATPG and SAR Functions
TVI(i)
TVO(i)
Cell Type
ATPG
SAR
Source of TDO
1
1 or 0
control
disable
TDO(i)
0
1
output
enable
disable
ATPG(i)
0
input
disable
enable
constant 0
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