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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 108/128頁 |
| 文件大?。?/td> | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
108
MC68HC912B32
MC68HC912B32TS/D
15 Analog-To-Digital Converter
The ATD is an 8-channel, 8-bit, multiplexed-input successive-approximation analog-to-digital converter,
accurate to
±
1 least significant bit (LSB). It does not require external sample and hold circuits because
of the type of charge redistribution technique used. The ATD converter timing is synchronized to the
system P clock. The ATD module consists of a 16-word (32-byte) memory-mapped control register
block used for control, testing and configuration.
Figure 26 Analog-to-Digital Converter Block Diagram
15.1 Functional Description
A single conversion sequence consists of four or eight conversions, depending on the state of the select
8 channel mode (S8CM) bit when ATDCTL5 is written. There are eight basic conversion modes. In the
non-scan modes, the SCF bit is set after the sequence of four or eight conversions has been performed
and the ATD module halts. In the scan modes, the SCF bit is set after the first sequence of four or eight
conversions has been performed, and the ATD module continues to restart the sequence. In both
modes, the CCF bit associated with each register is set when that register is loaded with the appropriate
conversion result. That flag is cleared automatically when that result register is read. The conversions
are started by writing to the control registers.
15.2 ATD Registers
ATDCTL0 —
Reserved
$0060
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
M
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
SAR
RC DAC ARRAY
AND COMPARATOR
INTERNAL BUS
V
DDA
V
SSA
V
RL
V
RH
CLOCK
SELECT/PRESCALE
ANALOG MUX
AND
SAMPLE BUFFER AMP
PORT AD
DATA INPUT REGISTER
AN7/PAD7
AN6/PAD6
AN5/PAD5
AN4/PAD4
AN3/PAD3
AN2/PAD2
AN1/PAD1
AN0/PAD0
REFERENCE
SUPPLY
HC12 ATD BLOCK
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