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參數(shù)資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 98/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
98
MC68HC912B32
MC68HC912B32TS/D
14 Byte Data Link Communications Module (BDLC)
The byte data link communications module (BDLC) provides access to an external serial communica-
tion multiplex bus, operating according to the SAE J1850 protocol.
14.1 Features
Features of the BDLC module include the following:
SAE J1850 compatible
10.4 Kbps VPW bit format
Digital noise filter
Collision detection
Hardware CRC generation and checking
Two power saving modes with automatic wake up on network activity
Polling and CPU interrupts with vector lookup available
Receive and transmit block mode supported
Supports 4X receive mode (41.6 Kbps)
Digital loopback mode
In-frame response (IFR) types 0, 1, 2, and 3 supported
Dedicated register for symbol timing adjustments
Digital module only, requires external analog transceiver
NOTE
It is recommended that the reader be familiar with the SAE Standard J1850 Class
B Data Communication Network Interfacespecification prior to proceeding with this
section.
14.2 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the power supplies, pins and the MCU.
Power Off
is entered from the reset mode whenever the BDLC supply voltage V
DD
drops below the min-
imum value for guaranteed operation. In this mode, the pin input and output specifications are not guar-
anteed.
Reset
is entered from the power off mode whenever the BDLC supply voltage V
DD
rises above its min-
imum specified value and an MCU reset source is asserted. To prevent the BDLC from entering an un-
known state, the internal MCU reset is asserted while powering up the BDLC. In reset mode, the internal
BDLC voltage references are operative, V
DD
is supplied to the internal circuits, which are held in their
reset state and the internal BDLC system clock is running. Registers will assume their reset condition.
Outputs are held in their programmed reset state. Inputs and network activity are ignored.
Run
is entered from the reset mode after all MCU reset sources are no longer asserted. It is entered
from the BDLC wait mode whenever activity is sensed on the J1850 bus. Run mode is entered from the
BDLC stop mode whenever network activity is sensed though messages will not be received properly
until the clocks have stabilized and the CPU is also in the run mode. In run mode, normal network op-
eration takes place. Ensure that all BDLC transmissions cease before exiting this mode.
BDLC Wait
power-conserving mode is automatically entered from the run mode whenever the CPU ex-
ecutes a WAIT instruction and if the WCM bit in the BCR register has been cleared. In this mode, the
BDLC internal clocks continue to run. The first passive-to-active transition of the bus wakes up the
BDLC and the CPU. If a valid byte is successfully received a CPU interrupt request will be generated.
BDLC Stop
power-conserving mode is automatically entered from the run mode whenever the CPU
executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM bit in the BCR
register has been set. In this mode, the BDLC internal clocks are stopped until network activity is sensed
and a CPU interrupt request is generated.
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