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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 26/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
26
MC68HC912B32
MC68HC912B32TS/D
Normal Single-Chip Mode
— There are no external address and data buses in this mode. All pins of
ports A, B and E are configured as general-purpose I/O pins. Port E bits 1 and 0 are input-only with
internal pull-ups and the other 22 pins are bidirectional I/O pins that are initially configured as high-im-
pedance inputs. Port E pull-ups are enabled upon reset; port A and B pull-ups are disabled upon reset.
5.1.2 Special Operating Modes
There are three special operating modes that correspond to normal operating modes. These operating
modes are commonly used in factory testing and system development. In addition, there is a special
peripheral mode, in which an external master, such as an I.C. tester, can control the on-chip peripher-
als.
Special Expanded Wide Mode
— This mode can be used for emulation of normal expanded wide
mode and emulation of normal single-chip mode and 16-bit data bus. The bus control related pins in
PORTE are all configured to serve their bus control output functions rather than general-purpose I/O.
Special Expanded Narrow Mode
— This mode can be used for emulation of normal expanded narrow
mode. In this mode external 16-bit data is handled as two back-to-back bus cycles, one for the high byte
followed by one for the low byte. Internal operations continue to use full 16-bit data paths.
Special Single-Chip Mode
— This mode can be used to force the MCU to active BDM mode to allow
system debug through the BKGD pin. The MCU does not fetch the reset vector and execute application
code as it would in other modes. Instead, the active background mode is in control of CPU execution
and BDM firmware is waiting for additional serial commands through the BKGD pin. There are no ex-
ternal address and data buses in this mode. The MCU operates as a stand-alone device and all program
and data space are on-chip. External port pins can be used for general-purpose I/O.
Special Peripheral Mode
— The CPU is not active in this mode. An external master can control on-
chip peripherals for testing purposes. It is not possible to change to or from this mode without going
through reset. Background debugging should not be used while the MCU is in special peripheral mode
as internal bus conflicts between BDM and the external master can cause improper operation of both
modes.
5.2 Background Debug Mode
Background debug mode (BDM) is an auxiliary operating mode that is used for system development.
BDM is implemented in on-chip hardware and provides a full set of debug operations. Some BDM com-
mands can be executed while the CPU is operating normally. Other BDM commands are firmware
based, and require the BDM firmware to be enabled and active for execution.
In special single-chip mode, BDM is enabled and active immediately out of reset. BDM is available in
all other operating modes, but must be enabled before it can be activated. BDM should not be used in
special peripheral mode because of potential bus conflicts.
Once enabled, background mode can be made active by a serial command sent via the BKGD pin or
execution of a CPU12 BGND instruction. While background mode is active, the CPU can interpret spe-
cial debugging commands, and read and write CPU registers, peripheral registers, and locations in
memory.
While BDM is active, the CPU executes code located in a small on-chip ROM mapped to addresses
$FF00 to $FFFF; BDM control registers are accessible at addresses $FF00 to $FF06. The BDM ROM
replaces the regular system vectors while BDM is active. While BDM is active, the user memory from
$FF00 to $FFFF is not in the map except through serial BDM commands.
BDM allows read and write access to internal memory-mapped registers and RAM, and read access to
EEPROM and Flash EEPROM without interrupting the application code executing in the CPU. This non-
intrusive mode uses dead bus cycles to access the memory and in most cases will remain cycle deter-
ministic. Refer to
16 Development Support
for more details on BDM.
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相關代理商/技術參數 |
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| MC68C812A4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Technical Supplement MC68C812A4 3.3V Electrical Characteristics |
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