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參數資料
型號： MC68B912B32
廠商： Motorola, Inc.
英文描述： 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述： 16位微控制器
文件頁數： 69/128頁
文件大小： 748K
代理商： MC68B912B32
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
69
Read and write anytime. A write will cause the PWM counter to reset to $00.
In special mode, if DISCR = 1, a write does not reset the PWM counter.
Each counter may be read any time without affecting the count or the operation of the corresponding
PWM channel. Writes to a counter cause the counter to be reset to $00 and force an immediate load of
both duty and period registers with new values. To avoid a truncated PWM period, write to a counter
while the counter is disabled. In left-aligned output mode, resetting the counter and starting the wave-
form output is controlled by a match between the period register and the value in the counter. In center-
aligned output mode the counters operate as up/down counters, where a match in period changes the
counter direction. The duty register changes the state of the output during the period to determine the
duty.
When a channel is enabled, the associated PWM counter starts at the count in the PWCNTx register
using the clock selected for that channel.
In special mode, when DISCP = 1 and configured for left-aligned output, a match of period does not
reset the associated PWM counter, and when configured center-aligned-output mode, a match of period
does not change the associated PWM counter direction.
Read and write anytime.
The value in the period register determines the period of the associated PWM channel. If written while
the channel is enabled, the new value will not take effect until the existing period terminates, forcing the
counter to reset. The new period is then latched and is used until a new period value is written. Reading
this register returns the most recent value written. To start a new period immediately, write the new pe-
riod value and then write the counter forcing a new period to start with the new period value.
Period = Channel-Clock-Period
/
(PWPER
+
1)
Period = Channel-Clock-Period
/
(2
×
(PWPER
+
1))
(CENTR = 0)
(CENTR = 1)
PWCNTx
— PWM Channel Counters
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT0
Bit 7
6
5
4
3
2
1
Bit 0
$0048
PWCNT1
Bit 7
6
5
4
3
2
1
Bit 0
$0049
PWCNT2
Bit 7
6
5
4
3
2
1
Bit 0
$004A
PWCNT3
Bit 7
6
5
4
3
2
1
Bit 0
$004B
RESET:
0
0
0
0
0
0
0
0
PWPERx
— PWM Channel Period Registers
Bit 7
6
5
4
3
2
1
Bit 0
PWPER0
Bit 7
6
5
4
3
2
1
Bit 0
$004C
PWPER1
Bit 7
6
5
4
3
2
1
Bit 0
$004D
PWPER2
Bit 7
6
5
4
3
2
1
Bit 0
$004E
PWPER3
Bit 7
6
5
4
3
2
1
Bit 0
$004F
RESET:
0
0
0
0
0
0
0
0
相關PDF資料
PDF描述
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MC68EC060 32-Bit Microprocessors.(32位微處理器)
相關代理商/技術參數
參數描述
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