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參數資料
型號: MC68B912B32
廠商: Motorola, Inc.
英文描述: 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述: 16位微控制器
文件頁數: 95/128頁
文件大小: 748K
代理商: MC68B912B32
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
95
Read anytime. Write anytime.
At reset, E Clock divided by 2 is selected.
SPR[2:0] — SPI Clock (SCK) Rate Select Bits
These bits are used to specify the SPI clock rate.
Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
SPIF is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SP0SR register
(with SPIF set) followed by an access (read or write) to the SPI data register.
WCOL — Write Collision Status Flag
The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated
because the error status flag can be read upon completion of the transfer that was in progress at the
time of the error. Automatically cleared by a read of the SP0SR (with WCOL set) followed by an access
NOTES:
1. The serial pin control 0 bit enables bidirectional configurations.
2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3)
3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4)
4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4)
5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)
Pin Mode
SPC0
1
MSTR
0
1
0
1
MISO
2
Slave Out
Master In
Slave I/O
GPI/O
MOSI
3
Slave In
Master Out
GPI/O
Master I/O
SCK
4
SCK In
SCK Out
SCK In
SCK Out
SS
5
SS In
SS I/O
SS In
SS I/O
#1
#2
#3
#4
Normal
0
Bidirectional
1
SP0BR
— SPI Baud Rate Registe
r
$00D2
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
SPR2
SPR1
SPR0
RESET:
0
0
0
0
0
0
0
0
Table 31 SPI Clock Rate Selection
SPR2
SPR1
SPR0
E Clock
Divisor
2
4
8
16
32
64
128
256
Frequency at
E Clock = 4 MHz
2.0 MHz
1.0 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.3 kHz
15.6 kHz
Frequency at
E Clock = 8 MHz
4.0 MHz
2.0 MHz
1.0 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.3 kHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SP0SR
— SPI Status Register
$00D3
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
WCOL
0
MODF
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
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