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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 70/128頁 |
| 文件大?。?/td> | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
70
MC68HC912B32
MC68HC912B32TS/D
Read and write anytime.
The value in each duty register determines the duty of the associated PWM channel. When the duty
value is equal to the counter value, the output changes state. If the register is written while the channel
is enabled, the new value is held in a buffer until the counter rolls over or the channel is disabled. Read-
ing this register returns the most recent value written.
If the duty register is greater than or equal to the value in the period register, there will be no duty change
in state. If the duty register is set to $FF the output will always be in the state which would normally be
the state opposite the PPOLx value.
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx
+
1)
/
(PWPERx
+
1)]
×
100%
Duty cycle = [(PWPERx
PWDTYx)
/
(PWPERx
+
1)]
×
100%
(PPOLx = 1)
(PPOLx = 0)
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx
PWDTYx)
/
(PWPERx
+
1)]
×
100%
Duty cycle = [(PWDTYx
+
1)
/
(PWPERx
+
1)]
×
100%
(PPOLx = 1)
(PPOLx = 0)
Read and write anytime.
PSWAI — PWM Halts while in Wait Mode
0 = Allows PWM main clock generator to continue while in wait mode.
1 = Halt PWM main clock generator when the part is in wait mode.
CENTR — Center-Aligned Output Mode
To avoid irregularities in the PWM output mode, write the CENTR bit only when PWM channels are dis-
abled.
0 = PWM channels operate in left-aligned output mode
1 = PWM channels operate in center-aligned output mode
RDPP — Reduced Drive of Port P
0 = All port P output pins have normal drive capability.
1 = All port P output pins have reduced drive capability.
PUPP — Pull-Up Port P Enable
0 = All port P pins have an active pull-up device disabled.
1 = All port P pins have an active pull-up device enabled.
PWDTYx
— PWM Channel Duty Registers
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY0
Bit 7
6
5
4
3
2
1
Bit 0
$0050
PWDTY1
Bit 7
6
5
4
3
2
1
Bit 0
$0051
PWDTY2
Bit 7
6
5
4
3
2
1
Bit 0
$0052
PWDTY3
Bit 7
6
5
4
3
2
1
Bit 0
$0053
RESET:
0
0
0
0
0
0
0
0
PWCTL —
PWM Control Register
$0054
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
PSWAI
CENTR
RDPP
PUPP
PSBCK
RESET:
0
0
0
0
0
0
0
0
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