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參數資料
型號: MC68B912B32
廠商: Motorola, Inc.
英文描述: 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述: 16位微控制器
文件頁數: 76/128頁
文件大小: 748K
代理商: MC68B912B32
MOTOROLA
76
MC68HC912B32
MC68HC912B32TS/D
Read or write anytime.
OMn — Output Mode
OLn — Output Level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a
successful OCn compare. When either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
These eight pairs of control bits configure the input capture edge detector circuits.
TCTL1
— Timer Control Register 1
$0088
Bit 7
6
5
4
3
2
1
Bit 0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
RESET:
0
0
0
0
0
0
0
0
TCTL2
— Timer Control Register 2
$0089
Bit 7
6
5
4
3
2
1
Bit 0
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
RESET:
0
0
0
0
0
0
0
0
Table 24 Compare Result Output Action
OMn
0
0
1
1
OLn
0
1
0
1
Action
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to zero
Set OCn output line to one
TCTL3
— Timer Control Register 3
$008A
Bit 7
6
5
4
3
2
1
Bit 0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
RESET:
0
0
0
0
0
0
0
0
TCTL4
— Timer Control Register 4
$008B
Bit 7
6
5
4
3
2
1
Bit 0
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
RESET:
0
0
0
0
0
0
0
0
Table 25 Edge Detector Circuit Configuration
EDGnB
0
0
1
1
EDGnA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
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