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參數資料
型號： MC68B912B32
廠商： Motorola, Inc.
英文描述： 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述： 16位微控制器
文件頁數： 52/128頁
文件大小： 748K
代理商： MC68B912B32
MOTOROLA
52
MC68HC912B32
MC68HC912B32TS/D
9 Resets and Interrupts
CPU12 exceptions include resets and interrupts. Each exception has an associated 16-bit vector, which
points to the memory location where the routine that handles the exception is located. Vectors are
stored in the upper 128 bytes of the standard 64-Kbyte address map.
The six highest vector addresses are used for resets and non-maskable interrupt sources. The remain-
der of the vectors are used for maskable interrupts, and all must be initialized to point to the address of
the appropriate service routine.
9.1 Exception Priority
A hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous
requests are made. Six sources are not maskable. The remaining sources are maskable, and any one
of them can be given priority over other maskable interrupts.
The priorities of the non-maskable sources are:
1.
2.
3.
4.
5.
6.
POR or RESET pin
Clock monitor reset
COP watchdog reset
Unimplemented instruction trap
Software interrupt instruction (SWI)
XIRQ signal (if X bit in CCR = 0)
9.2 Maskable Interrupts
Maskable interrupt sources include on-chip peripheral systems and external interrupt service requests.
Interrupts from these sources are recognized when the global interrupt mask bit (I) in the CCR is
cleared. The default state of the I bit out of reset is one, but it can be written at any time.
Interrupt sources are prioritized by default but any one maskable interrupt source may be assigned the
highest priority by means of the HPRIO register. The relative priorities of the other sources remain the
same.
An interrupt that is assigned highest priority is still subject to global masking by the I bit in the CCR, or
by any associated local bits. Interrupt vectors are not affected by priority assignment. HPRIO can only
be written while the I bit is set (interrupts inhibited).
Table 17
lists interrupt sources and vectors in default
order of priority.
Table 17 Interrupt Vector Map
Vector Address
Interrupt Source
CCR
Mask
None
None
None
None
None
X bit
I bit
I bit
I bit
I bit
I bit
Local Enable
Register (Bit)
None
COPCTL (CME, FCME)
COP rate selected
None
None
None
INTCR (IRQEN)
RTICTL (RTIE)
TMSK1 (C0I)
TMSK1 (C1I)
TMSK1 (C2I)
HPRIO Value to
Elevate
–
–
–
–
–
–
$F2
$F0
$EE
$EC
$EA
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
Reset
COP clock monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real time interrupt
Timer channel 0
Timer channel 1
Timer channel 2
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