
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
93
13.3.3 SS Output
Available in master mode only, SS output is enabled with the SSOE bit in the SP0CR1 register if the
corresponding DDRS bit is set. The SS output pin will be connected to the SS input pin of the external
slave device. The SS output automatically goes low for each transmission to select the external device
and it goes high during each idling state to deselect external devices.
13.3.4 Bidirectional Mode (MOMI or SISO)
In bidirectional mode, the SPI uses only one serial data pin for external device interface. The MSTR bit
decides which pin to be used. The MOSI pin becomes serial data I/O (MOMI) pin for the master mode,
and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The direction of each serial
I/O pin depends on the corresponding DDRS bit.
Figure 24 Normal Mode and Bidirectional Mode
13.3.5 Register Descriptions
Control and data registers for the SPI subsystem are described below. The memory address indicated
for each register is the default address that is in use after reset. The entire 512-byte register block can
be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. For more information
refer to
5 Operating Modes and Resource Mapping
.
Table 30 SS Output Selection
DDS7
0
0
1
1
SSOE
0
1
0
1
Master Mode
Slave Mode
SS Input
SS Input
SS Input
SS Input
SS Input with MODF Feature
Reserved
General-Purpose Output
SS Output
When SPE=1
Master Mode
MSTR=1
Slave Mode
MSTR=0
Normal
Mode
SPC0=0
SWOM enables open drain output.
SWOM enables open drain output.
Bidirectional
Mode
SPC0=1
SWOM enables open drain output. PS4 becomes GPIO.
SWOM enables open drain output. PS5 becomes GPIO.
SP0CR1
— SPI Control Register 1
$00D0
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
SWOM
MSTR
CPOL
CPHA
SSOE
LSBF
RESET:
0
0
0
0
0
1
0
0
SPI
MO
MI
DDS5
Serial Out
Serial In
SPI
SI
SO
Serial In
Serial Out
DDS4
SPI
MOMI
PS4
DDS5
Serial Out
Serial In
SPI
PS5
SISO
DDS4
Serial In
Serial Out