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參數資料
型號: MC68B912B32
廠商: Motorola, Inc.
英文描述: 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述: 16位微控制器
文件頁數: 18/128頁
文件大小: 748K
代理商: MC68B912B32
MOTOROLA
18
MC68HC912B32
MC68HC912B32TS/D
Table 6 MC68HC912B32 Port Description Summary
Port Name
Port A
PA[7:0]
Pin
Numbers
Data Direction
DD Register (Address)
In/Out
DDRA ($0002)
Description
46–39
Port A and port B pins are used for
address
and
data
in ex-
panded modes. The port data registers are not in the address
map during expanded and peripheral mode operation. When
in the map, port A and port B can be read or written any time.
DDRA and DDRB are not in the address map in expanded or
peripheral modes.
Port B
PB[7:0]
25–18
In/Out
DDRB ($0003)
Port AD
PAD[7:0]
Port DLC
PDLC[6:0]
58–51
In
Analog-to-digital converter
and general-purpose I/O.
70–76
In/Out
DDRDLC ($00FF)
PE[1:0] In
PE[7:2] In/Out
DDRE ($0009)
In/Out
DDRP ($0057)
In/Out
DDRS ($00D7)
Byte Data Link Communication
(BDLC) subsystem and
general-purpose I/O.
Port E
PE[7:0]
26–29, 35–38
Mode selection
,
bus control
signals and
interrupt service
request
signals; or general-purpose I/O.
Port P
PP[7:0]
Port S
PS[7:0]
79, 80, 1–6
General-purpose I/O. PP[3:0] are use with the
pulse-width
modulator
when enabled.
Serial communications interface
and
serial peripheral in-
terface
subsystems and general-purpose I/O.
General-purpose I/O when not enabled for input capture and
output compare in the
timer
and
pulse accumulator
sub-
system.
68–61
Port T
PT[7:0]
16–12, 9–7
In/Out
DDRT ($00AF)
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