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參數(shù)資料
型號(hào)： MC68CK338
廠商： Motorola, Inc.
元件分類： 32位微控制器
英文描述： Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述： 高度集成，低功耗，32位微控制器
文件頁數(shù)： 100/133頁
文件大小： 798K
代理商： MC68CK338
MOTOROLA
100
MC68CK338
MC68CK338TS/D
FLAG — Event Flag
This status bit indicates whether or not an input capture or output compare event has occurred. If the
IL[2:0] field is non-zero, an interrupt request is generated when FLAG is set.
0 = An input capture or output compare event has not occurred
1 = An input capture or output compare event has occurred
Table 56
shows the event flag status during different modes.
FLAG is set only by hardware and cleared by software or by a system reset. To clear the bit, first read
the register with FLAG set to one, then write a zero to the bit. Placing the DASM in DIS mode will also
clear the flag.
NOTE
The flag clearing mechanism works only if no flag setting event occurs between the
read and write operations. If a FLAG setting event occurs between the read and
write operations, the FLAG bit will not be cleared.
IL[2:0] — Interrupt Level
Setting IL[2:0] to a non-zero value causes the DASM to request an interrupt when the FLAG bit sets. If
IL[2:0] = %000, no interrupt will be requested when FLAG sets.
IARB3 — Interrupt Arbitration Bit 3
This bit works in conjunction with IARB[2:0] in the BIUMCR. Each module that generates interrupt re-
quests on the IMB must have a unique value in the arbitration field. This interrupt arbitration identifica-
tion number is used to arbitrate for the IMB when modules generate simultaneous interrupts of the same
priority. The IARB3 bit is cleared by reset. Refer to
6.4.1 BIUSM Registers
for more information on
IARB[2:0].
WOR — Wired-OR Mode
In the DIS, IPWM, IPM and IC modes, WOR is not used. Reading this bit returns the value that was
previously written.
In the OCB, OCAB and OPWM modes, WOR selects whether the output buffer is configured for normal
or open drain operation.
0 = Output buffer operates in normal mode
1 = Output buffer operates in open drain mode
BSL — Bus Select
This bit selects the time base bus connected to the DASM.
0 = DASM is connected to time base bus A.
1 = DASM is connected to time base bus B.
Table 60 Event Flag Status Conditions
Mode
DIS
IPWM
IPM
IC
OCB
OCAB
OPWM
Status Description
FLAG bit is cleared
FLAG bit is set each time there is a capture on channel A
FLAG bit is set each time there is a capture on channel A, except for the first time
FLAG bit is set each time there is a capture on channel A
FLAG bit is set each time there is a successful comparison on channel B
FLAG bit is set each time there is a successful comparison on either channel A or B
FLAG bit is set each time there is a successful comparison on channel A
相關(guān)PDF資料
PDF描述
MC68EC060 32-Bit Microprocessors.(32位微處理器)
MC68EN360RC25V QUad Integrated Communications Controller Users Manual
MC68EN360CFE25 QUad Integrated Communications Controller Users Manual
MC68EN360FE25 AC 4C 4#12 PIN PLUG 023
MC68EN360FE25V QUad Integrated Communications Controller Users Manual
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MC68CK338CPV14B1 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:32-Bit Modular Microcontroller
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MC68CM16Z1CFC16 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series
MC68CM16Z1CPV16 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series
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