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參數資料
型號: MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁數: 43/133頁
文件大小: 798K
代理商: MC68CK338
MC68CK338
MC68CK338TS/D
MOTOROLA
43
3.8.3 Functions of Pins for Other Modules During Reset
Generally, pins associated with modules other than the SIML default to port functions, and input/output
ports are set to input state. This is accomplished by disabling pin functions in the appropriate control
registers, and by clearing the appropriate port data direction registers. Refer to individual module sec-
tions in this manual for more information.
3.8.4 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIML pins are either in a disabled high-impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
Table 32 SIML Pin Reset States
Pin(s)
Pin State
While RESET
Asserted
Pin State After RESET Released
Default Function
Pin Function
Pin State
V
DD
V
DD
ADDR[18:0]
Unknown
AS
Output
AVEC
Input
BERR
Input
V
DD
V
DD
V
DD
CLKOUT
Output
V
SS
DATA[15:0]
Input
DS
Output
DSACK0
Input
DSACK1
Input
V
DD
HALT
Input
IRQ[7:1]
Input
MODCLK
Input
R/W
Output
RESET
Input
RMC
Output
SIZ[1:0]
Unknown
TSC
Input
Alternate Function
Pin Function
Pin State
CS10/ADDR23/ECLK
V
DD
V
DD
High-Z
High-Z
High-Z
High-Z
V
DD
V
DD
V
DD
Output
V
DD
Mode select
High-Z
High-Z
High-Z
V
DD
High-Z
High-Z
Mode Select
High-Z
Asserted
High-Z
High-Z
Mode select
CS10
ADDR23
Unknown
CS[9:6]/ADDR[22:19]/PC[6:3]
CS[9:6]
ADDR[22:19]
Unknown
ADDR[18:0]
AS/PE5
AVEC/PE2
BERR
ADDR[18:0]
PE5
PE2
BERR
Unknown
Input
Input
Input
V
DD
CS1/BG
CS1
BG
CS2/BGACK
CS2
BGACK
Input
CS0/BR
CS0
BR
Input
CLKOUT
CLKOUT
Output
V
SS
Input
Input
Input
Input
CSBOOT
CSBOOT
CSBOOT
DATA[15:0]
DS/PE4
DSACK0/PE0
DSACK1/PE1
DATA[15:0]
PE4
PE0
PE1
CS[5:3]/FC[2:0]/PC[2:0]
CS[5:3]
FC[2:0]
Unknown
HALT
HALT
PF[7:1]
PF0
R/W
RESET
PE3
PE[7:6]
TSC
Input
Input
Input
Output
Input
Input
Input
Input
IRQ[7:1]/PF[7:1]
MODCLK/PF0
R/W
RESET
RMC/PE3
SIZ[1:0]/PE[7:6]
TSC
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