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參數資料
| 型號： | MC68CK338 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數： | 20/133頁 |
| 文件大小： | 798K |
| 代理商： | MC68CK338 |
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MOTOROLA
20
MC68CK338
MC68CK338TS/D
3.3.5 Low-Power Operation
Low-power operation is initiated by the CPU32L. To reduce power consumption selectively, the
CPU32L can enter the following low-power modes:
1.
2.
3.
The CPU32L can selectively disable a module by setting the module’s STOP bit.
The CPU32L can execute the STOP instruction.
The CPU32L can execute the LPSTOP instruction to stop the operations of only the CPU32L
or the entire MCU, including the CPU32L.
If the STOP bit in a module is set, then that module enters a low power mode. Some or all of that mod-
ule’s registers remain accessible. The module can be restarted by asserting RESET or by the CPU32L
clearing the module’s STOP bit.
The CPU32L can enter a low power mode by executing the STOP instruction. It can be reawakened by
RESET, trace or interrupt.
3.3.5.1 Normal LPSTOP mode
This low-power stop mode offers the greatest power reduction. To enter normal LPSTOP mode, the
CPU32L executes the LPSTOP instruction after clearing the STCPU bit in SYNCR. This causes the
SIML to turn off the system clock to most of the MCU.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the current interrupt
mask into the clock control logic. The SIML brings the MCU out of normal LPSTOP mode when one of
the following exceptions occurs:
RESET
Trace
SIML interrupt of higher priority than the stored interrupt mask
During a LPSTOP, unless the system clock signal is supplied by an external source and that source is
removed, the SIML clock control logic and the SIML clock signal (SIMCLK) continue to operate. The
periodic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK, and can
be used to bring the processor out of LPSTOP. The software watchdog monitor cannot perform this
function. Optionally, the SIML can also continue to generate the CLKOUT signal while in LPSTOP.
STSIM and STEXT bits in SYNCR determine clock operation during LPSTOP.
3.3.5.2 Modified LPSTOP mode
To enter modified LPSTOP mode, the CPU32L first sets the STCPU bit in SYNCR, then executes the
LPSTOP instruction. This causes the SIML to turn off the system clock to the CPU32L only. The other
MCU modules continue to operate. The SIML brings the MCU out of normal LPSTOP mode when one
of the following exceptions occurs:
RESET
Trace
Interrupt of higher priority than the stored interrupt mask from any MCU module
This low-power stop mode offers better power reduction than using the STOP instruction since the clock
in the CPU32L is held inactive. Also, the STOP bits of individual modules may be set or cleared, leaving
some active and others inactive. The flow chart shown in
Figure 8
summarizes the effects of the
STCPU, STSIM, and STEXT bits when the MCU enters normal or modified LPSTOP mode.
NOTE
To keep power consumption to a minimum when in LPSTOP mode, do not allow
any spurious interrupts to occur. If a spurious interrupt occurs during LPSTOP
mode, the device will transition to the STOP mode (which has greater power
consumption) until a non-spurious interrupt request is detected by the CPU32L.
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相關代理商/技術參數 |
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| MC68CM16Z1CFC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
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