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參數資料
型號: MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁數: 60/133頁
文件大?。?/td> 798K
代理商: MC68CK338
MOTOROLA
60
MC68CK338
MC68CK338TS/D
STOP — Stop Enable
0 = Normal QSM clock operation
1 = QSM clock operation stopped
STOP places the QSM in a low-power state by disabling the system clock in most parts of the module.
The QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is
not readable. However, writes to RAM or any register are guaranteed to be valid while STOP is assert-
ed. STOP can be negated by the CPU and by reset.
The system software must stop each submodule before asserting STOP to avoid complications at re-
start and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and
the operation should be verified for completion before asserting STOP. The QSPI submodule should be
stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set.
FRZ1 — Freeze 1
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted.
FREEZE is asserted whenever the CPU enters the background mode.
FRZ0 — Freeze 0
Reserved
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted
0 = User access
1 = Supervisor access
SUPV defines the assignable QSM registers as either supervisor-only data space or unrestricted data
space.
IARB — Interrupt Arbitration Identification Number
The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each
module that can generate interrupt requests must be assigned a unique, non-zero IARB field value.
Refer to
3.9 Interrupts
for more information.
QTEST —
QSM Test Register
QTEST is used during factory testing of the QSM. Accesses to QTEST must be made while the MCU
is in test mode.
$YFFC02
QILR determines the priority level of interrupts requested by the QSM and the vector used when an in-
terrupt is acknowledged.
ILQSPI — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
QILR —
QSM Interrupt Levels Register
$YFFC04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
ILQSPI
ILSCI
QIVR
RESET:
0
0
0
0
0
0
0
0
相關PDF資料
PDF描述
MC68EC060 32-Bit Microprocessors.(32位微處理器)
MC68EN360RC25V QUad Integrated Communications Controller Users Manual
MC68EN360CFE25 QUad Integrated Communications Controller Users Manual
MC68EN360FE25 AC 4C 4#12 PIN PLUG 023
MC68EN360FE25V QUad Integrated Communications Controller Users Manual
相關代理商/技術參數
參數描述
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