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參數資料
型號: MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁數: 30/133頁
文件大小: 798K
代理商: MC68CK338
MOTOROLA
30
MC68CK338
MC68CK338TS/D
3.6 Chip-Selects
Typical microcontrollers require additional hardware to provide external chip-select and address de-
code signals. The MC68338 includes 12 programmable chip-selects that can provide 2 to 16-clock-cy-
cle access to external memory and peripherals. Address block sizes of two Kbytes to one Mbyte can be
selected.
Figure 11
is a functional diagram of a chip-select circuit.
Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write
strobe, or interrupt acknowledge signals. Chip-select logic can also generate DSACK and AVEC signals
internally. Each signal can also be synchronized with the ECLK signal available on ADDR23.
Figure 11 Chip-Select Circuit Block Diagram
NOTES:
1. All transfers are aligned. The CPU32L does not support misaligned word or long-word transfers.
2. Operands in parentheses are ignored by the CPU32L during read cycles.
3. 3-Byte transfer cases occur only as a result of a long word to 8-bit port transfer.
Table 16 Operand Alignment
Current
Cycle
1
2
3
4
5
6
7
8
9
Transfer Case
1
SIZ1
SIZ0
ADDR0
DSACK1 DSACK0
DATA
[15:8]
OP0
OP0
OP0
(OP0)
OP0
OP0
OP0
OP0
OP0
DATA
[7:0]
(OP0)
2
(OP0)
(OP0)
OP0
(OP1)
OP1
(OP0)
(OP0)
OP1
Next
Cycle
2
5
7
6
Byte to 8-bit port (even)
Byte to 8-bit port (odd)
Byte to 16-bit port (even)
Byte to 16-bit port (odd)
Word to 8-bit port
Word to 16-bit port
3-byte to 8-bit port
3
Long word to 8-bit port
Long word to 16-bit port
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
1
0
0
1
0
1
1
0
0
0
1
1
0
1
0
0
1
CHIP SEL BLOCK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
BASE ADDRESS REGISTER
TIMING
AND
CONTROL
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
AVEC
DSACK
PIN
BUS CONTROL
INTERNAL
SIGNALS
ADDRESS
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相關代理商/技術參數
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