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參數(shù)資料
型號: MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁數(shù): 131/133頁
文件大小: 798K
代理商: MC68CK338
MC68CK338
MC68CK338TS/D
MOTOROLA
131
NOTES:
1. All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
3. Data can be recognized properly with longer transition times as long as MOSI/MISO signals from external
sources are at valid V
OH
/V
OL
prior to SCK transitioning between valid V
OL
and V
OH
. Due to process variation,
logic decision point voltages of the data and clock signals can differ, which can corrupt data if slower transition
times are used.
Table 74 QSPI Timing
(V
DD
and V
DDSYN
= 2.7 to 3.6 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
200 pF load on all QSPI pins)
1
Num
Function
Symbol
Min
Max
Unit
1
Operating Frequency
Master
Slave
f
op
DC
DC
1/4
1/4
System Clock Frequency
System Clock Frequency
2
Cycle Time
Master
Slave
t
qcyc
4
4
510
t
cyc
t
cyc
3
Enable Lead Time
Master
Slave
t
lead
2
2
128
t
cyc
t
cyc
4
Enable Lag Time
Master
Slave
t
lag
2
1/2
SCK
t
cyc
5
Clock (SCK) High or Low Time
Master
Slave
2
t
sw
2 t
cyc
– 60
2 t
cyc
– n
255 t
cyc
ns
ns
6
Sequential Transfer Delay
Master
Slave (Does Not Require Deselect)
t
td
17
13
8192
t
cyc
t
cyc
7
Data Setup Time (Inputs)
Master
Slave
t
su
45
30
ns
ns
8
Data Hold Time (Inputs)
Master
Slave
t
hi
0
30
ns
ns
9
Slave Access Time
t
a
1
t
cyc
10
Slave MISO Disable Time
t
dis
2
t
cyc
11
Data Valid (after SCK Edge)
Master
Slave
t
v
75
75
ns
ns
12
Data Hold Time (Outputs)
Master
Slave
t
ho
0
0
ns
ns
13
Rise Time
Input
Output
t
ri
t
ro
2
45
μ
s
ns
14
Fall Time
Input
3
Output
t
fi
t
fo
2
45
μ
s
ns
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