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參數資料
| 型號： | MC68CK338 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數： | 89/133頁 |
| 文件大小： | 798K |
| 代理商： | MC68CK338 |
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MC68CK338
MC68CK338TS/D
MOTOROLA
89
IL[2:0] — Interrupt Level
Setting IL[2:0] to a non-zero value causes the FCSM to request an interrupt of the selected level when
the COF bit sets. If IL[2:0] = %000, no interrupt will be requested when COF sets. These bits can be
read or written at any time and are cleared by reset.
IARB3 — Interrupt Arbitration Bit 3
This bit works in conjunction with IARB[2:0] in the BIUMCR. Each module that generates interrupt re-
quests on the IMB must have a unique value in the arbitration field. This interrupt arbitration identifica-
tion number is used to arbitrate for the IMB when modules generate simultaneous interrupts of the same
priority. The IARB3 bit is cleared by reset. Refer to
6.4.1 BIUSM Registers
for more information on
IARB[2:0].
DRV[A:B] — Drive Time Base Bus
This bit field contains read/write bits that control the connection of the FCSM to the time base buses A
and B. These bits are cleared by reset. Refer to
Table 52
.
WARNING
Two time base buses should not be driven at the same time.
IN — Input Pin Status Bit
This read-only status bit reflects the logic state of the FCSM input pin. Writing to this bit has no effect,
nor does reset.
NOTE
The clock input of FCSM3 is internally connected to I/O pin CTD27 of DASM27 and
will read the state of that pin.
CLK[2:0] — Counter Clock Select
These read/write control bits select one of six internal clock signals (PCLK[1:6]) or one of two external
conditions on the external clock input pin. Maximum frequency of the external clock signals is f
sys
/4.
Refer to
Table 54
.
Table 50 Drive Time Base Bus Field
DRVA
0
0
1
1
DRVB
0
1
0
1
Bus Selected
No time base bus driven
Time base bus B is driven
Time base bus A is driven
Both time base buses A and B are driven
Table 51 Counter Clock Select Field
CLK2
CLK1
CLK0
Free-Running Counter Clock Source
PCLK1 (f
sys
÷
2 or f
sys
÷
3)
PCLK2 (f
sys
÷
4 or f
sys
÷
6)
PCLK3 (f
sys
÷
8 or f
sys
÷
12)
PCLK4 (f
sys
÷
16 or f
sys
÷
24)
PCLK5 (f
sys
÷ 3
2 or f
sys
÷
48)
PCLK6 (f
sys
÷
64 or f
sys
÷
768)
External clock input, falling edge
External clock input, rising edge
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
0
1
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