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參數資料
型號: MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁數: 74/133頁
文件大小: 798K
代理商: MC68CK338
MOTOROLA
74
MC68CK338
MC68CK338TS/D
SCCR1 contains SCI configuration parameters. The CPU can read and write this register at any time.
The SCI can modify RWU in some circumstances. In general, interrupts enabled by these control bits
are cleared by reading SCSR, then reading (for receiver status bits) or writing (for transmitter status bits)
SCDR.
Bit 15 — Not Implemented
LOOPS — Loop Mode
0 = Normal SCI operation, no looping, feedback path disabled
1 = Test SCI operation, looping, feedback path enabled
LOOPS controls a feedback path on the data serial shifter. When loop mode is enabled, SCI transmitter
output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver
must be enabled before entering loop mode.
WOMS — Wired-OR Mode for SCI Pins
0 = If configured as an output, TXD is a normal CMOS output.
1 = If configured as an output, TXD is an open-drain output.
WOMS determines whether the TXD pin is an open-drain output or a normal CMOS output. This bit is
used only when TXD is an output. If TXD is used as a general-purpose input pin, WOMS has no effect.
ILT — Idle-Line Detect Type
0 = Short idle-line detect (start count on first one)
1 = Long idle-line detect (start count on first one after stop bit(s))
PT — Parity Type
0 = Even parity
1 = Odd parity
When parity is enabled, PT determines whether parity is even or odd for both the receiver and the trans-
mitter.
PE — Parity Enable
0 = SCI parity disabled
1 = SCI parity enabled
PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the re-
ceived parity bit is not correct, the SCI sets the PF error flag in SCSR.
When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which re-
sults in either seven or eight bits of user data, depending on the condition of M bit.
Table 44
lists the
available choices.
SCCR1 —
SCI Control Register 1
$YFFC0A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
LOOPS
WOMS
ILT
PT
PE
M
WAKE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 44 Parity Enable Data Bit Selection
M
0
0
1
1
PE
0
1
0
1
Result
8 data bits
7 data bits, 1 parity bit
9 data bits
8 data bits, 1 parity bit
相關PDF資料
PDF描述
MC68EC060 32-Bit Microprocessors.(32位微處理器)
MC68EN360RC25V QUad Integrated Communications Controller Users Manual
MC68EN360CFE25 QUad Integrated Communications Controller Users Manual
MC68EN360FE25 AC 4C 4#12 PIN PLUG 023
MC68EN360FE25V QUad Integrated Communications Controller Users Manual
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