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參數(shù)資料
型號: MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁數(shù): 57/133頁
文件大小: 798K
代理商: MC68CK338
MC68CK338
MC68CK338TS/D
MOTOROLA
57
5 Queued Serial Module
The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial
communication interface (SCI).
Figure 14
shows the QSM block diagram.
Figure 14 QSM Block Diagram
5.1 Overview
The QSPI provides easy peripheral expansion or interprocessor communication through a full-duplex,
synchronous, three-line bus: data in, data out, and a serial clock. Four programmable peripheral chip-
select pins provide addressability for up to 16 peripheral devices. A self-contained RAM queue allows
up to 16 serial transfers of 8 to 16 bits each, or transmission of a 256-bit data stream without CPU in-
tervention. A special wraparound mode supports continuous sampling of a serial peripheral, with auto-
matic QSPI RAM updating, which makes the interface to A/D converters more efficient.
The SCI provides a standard non-return to zero (NRZ) mark/space format. It operates in either full- or
half-duplex mode. There are separate transmitter and receiver enable bits and dual data buffers. A
modulus-type baud rate generator provides rates from 55 to 451 kbaud with a 14.44-MHz system clock.
Word length of either eight or nine bits is software selectable. Optional parity generation and detection
provide either even or odd parity check capability. Advanced error detection circuitry catches glitches
of up to 1/16 of a bit time in duration. Wakeup functions allow the CPU to run uninterrupted until mean-
ingful data is available.
Table 35
shows the address map of the QSM.
QSPI
INTERFACE
LOGIC
SCI
MISO/PQS0
MOSI/PQS1
SCK/PQS2
PCS0/SS/PQS3
PCS1/PQS4
PCS2/PQS5
PCS3/PQS6
TXD/PQS7
RXD
P
QSM BLOCK
I
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