
MOTOROLA
106
MC68CK338
MC68CK338TS/D
NOTE
TICKF is only cleared if the 32-bit free-running counter does not increment be-
tween reading RTC16SIC with TICKF set to one and then writing TICKF to zero.
IL[2:0] — Interrupt Level Field
Setting IL[2:0] to a non-zero value causes the RTCSM to request an interrupt of the selected level when
the TICKF bit sets. If IL[2:0] = %000, no interrupt will be requested when TICKF sets.
IARB3 — Interrupt Arbitration Bit 3
This bit works in conjunction with IARB[2:0] in the BIUMCR. Each module that generates interrupt re-
quests on the IMB must have a unique value in the arbitration field. This interrupt arbitration identifica-
tion number is used to arbitrate for the IMB when modules generate simultaneous interrupts of the same
priority. The IARB3 bit is cleared by reset. Refer to
6.4.1 BIUSM Registers
for more information on
IARB[2:0].
WEN — Write Enable Control
This bit allows the 15-bit prescaler and the 32-bit free-running counter to be updated. Normally, these
are read-only registers. Regular write operations have no effect. When the WEN bit is written to one, it
sets a latch that allows the 15-bit prescaler and the 32-bit free-running counter to be written. The latch
is automatically reset when the prescaler is written.
To write a new value to the complete counter chain:
Write a one to the WEN bit.
Execute a long-word write to the 32-bit free-running counter high (R16FRCH) register.
Execute a word write to the 15-bit prescaler (R16PRR) register.
WEN cannot be written to one again until the writes to update the prescaler and free-running counter
have been completed. The WEN bit always reads as zero.
EN — RTCSM Enable
This bit selects whether the RTCSM is running or not.
0 = RTCSM is not running
1 = RTCSM is running
The EN bit is not affected by reset. If the RTCSM is not to be used, it is recommended that EN be
cleared as soon as the MCU comes out of reset.
R16PRR contains the synchronized value of the 15-bit prescaler or the value to be loaded into the 15-
bit prescaler.
NOTE
When the RTCSM is disabled, writing to the 15-bit prescaler and 32-bit free-
running counter may give unpredictable results.
R16PRR —
RTCSM Prescaler Register
$YFF482
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET:
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0