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參數資料
| 型號： | MR82510 |
| 廠商： | Intel Corp. |
| 英文描述： | ASYNCHRONOUS SERIAL CONTROLLER |
| 中文描述： | 異步串行控制器 |
| 文件頁數： | 11/40頁 |
| 文件大小： | 463K |
| 代理商： | MR82510 |
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M82510
Table 7. Standard Baud Rates
Bit Rate
16x Divisor
%
Error
110
5236 (1474h)
.007%
300
1,920 (780h)
D
1200
480 (1E0h)
D
2400
240 (F0h)
D
9600
60 (3Ch)
D
19,200
30 (1Eh)
D
38,400
15 (0Fh)
D
56,000
10 (0Ah)
2.8%
288,000
2 (02h)
D
Source CLK
e
Internal Sys. Clk
e
18.432 MHz/2
e
9.216 MHz
The BRG counts down in increments of two and
then is divided by two to generate a 50% duty cycle;
however, for odd divisors it will count down the first
time by one. All subsequent countdowns will then
continue in steps of two. In those cases the duty
cycle is no longer exactly 50%. The deviation is giv-
en by the following equation:
deviation
e
1/(2
X
divisor)
The BRG can operate with any divisor between 1
and 65,535; however, for divisors between 1 and 3
the duty cycle is as follows:
Table 8. Duty Cycles
Divisor
Duty Cycle
3
33%
2
50%
1
Same as Source
0
FORBIDDEN
Timer Mode
Each of the M82510 BRGs can be used as Timers.
The Timer is used to generate time delays by count-
ing the internal system clock. When enabled the
Timer uses the count from the Divisor/Count regis-
ters to count down to 1. Upon terminal count a
maskable Timer Expired interrupt is generated. The
delay between the trigger and the terminal count is
given by the following equation:
Delay
e
Count
X
(System Clock Period)
To start counting, the Timer has to be triggered via
the Start Timer Command. To restart the Timer after
terminal count or while counting, the software has to
issue the trigger command again. While counting the
Timer can be enabled or disabled by using a soft-
ware controlled Gate. It is also possible to output a
pulse generated upon terminal count through the TA
or TB pins.
In 1X clock mode the only clock source available is
the SCLK pin. The serial machines (both Tx Machine
and Rx Machine) can independently use one of two
clock modes, either 1X or 16X. Also no configuration
changes are allowed during operation as each write
in the BRG configuration registers causes a reset
signal to be sent to the BRG logic. The mode or
source clocks may be changed only after a Hard-
ware or Software reset. The Divisor (or count, de-
pending upon the mode) may be updated during op-
eration unless the particular BRG machine is being
used as a clock source for one of the serial ma-
chines, and the particular serial machine is in opera-
tion at the time. Loading the count registers with ‘‘0’’
is forbidden in all cases, and loading it with a ‘‘1’’ is
forbidden in the Timer Mode only.
SERIAL DIAGNOSTICS
The M82510 supports two modes of Loopback oper-
ation, Local Loopback and Remote Loopback as
well as an Echo mode for diagnostics and improved
throughput.
LOCAL LOOPBACK
271072–11
Figure 12. Local Loopback
The Tx Machine output and Rx Machine input are
shorted internally, TXD pin output is held at Mark.
This feature allows simulation of Transmission/Re-
ception of characters and checks the Tx FIFO, Tx
Machine, Rx Machine, and Rx FIFO along with the
software without any external side effects. The mo-
dem outputs OUT1, OUT2, DTR and RTS are inter-
nally shorted to RI, DCD, DSR and CTS respectively.
OUT0 is held at a mark state.
11
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相關代理商/技術參數 |
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