
M82510
23. RSTDRECEIVE MACHINE STATUS REGISTER
RSTDReceive Machine Status Register
271072–36
This register displays the status of the Receive Ma-
chine. It reports events that have occurred since the
RST was cleared. This register is cleared when it is
read except for BIT0, Rx FIFO interrupt. Each bit in
this register, when set, can cause an interrupt. Five
bits of this register are shared with the LSR register.
CRFDControl/Address
When enabled, this bit can cause an interrupt if a
control character or address character is received.
Character
ReceivedD
In uLAN Mode: indicates that an address charac-
ter has been received.
In normal Mode: indicates that a standard control
character (either ASCII or EBCDIC) has been re-
ceived.
PCRFDProgrammed Control/Address Character
ReceivedD
This bit, when enabled, will cause an in-
terrupt when an address or control character match
occurs.
In uLAN Mode: indicates that an address charac-
ter equal to one of the registers ACR0 or ACR1
has been received.
In normal Mode: indicates that a character which
matches the registers ACR0 or ACR1 has been
received.
BkTDBreak TerminatedD
This bit indicates that a
break condition has been terminated.
BkDDBreak DetectedD
This bit indicates that a
Break Condition has been detected, i.e., RxD input
was held low for one character frame plus a stop
BIT.
FEDFraming ErrorD
This bit indicates that a re-
ceived character did not have a valid stop bit.
PEDParity ErrorD
Indicates that a received charac-
ter had a parity error.
OEDOverrun ErrorD
Indicates that a received
character was lost because the Rx FIFO was full.
RFIRDReceive FIFO Interrupt RequestD
Same
as the RFIR bit of LSR register.
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