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參數資料
| 型號： | MR82510 |
| 廠商： | Intel Corp. |
| 英文描述： | ASYNCHRONOUS SERIAL CONTROLLER |
| 中文描述： | 異步串行控制器 |
| 文件頁數： | 33/40頁 |
| 文件大小： | 463K |
| 代理商： | MR82510 |
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M82510
30. RCMDRECEIVE COMMAND REGISTER
RCMDReceive Command Register
271072–43
This register controls the operation of the Rx ma-
chine.
RxEDReceive EnableD
Enables the reception of
characters.
RxDiDReceive
data on RXD pin.
DisableD
Disables
reception
of
FRMDFlush Receive MachineD
Resets the Rx
Machine logic (but not registers and FIFOs), enables
reception, and unlocks the receive FIFO.
FRFDFlush Receive FIFOD
Clears the Rx FIFO.
LRFDLocks Rx FIFOD
Disables the write mecha-
nism of the Rx FIFO so that characters subsequently
received are not written to the Rx FIFO but are lost.
However, reception is not disabled and complete
status/event reporting continues. (This command
may be used in the uLAN mode to disable loading of
characters into the Rx FIFO until an address match
is detected.)
ORFDOpen (Unlock) Rx FIFOD
This command en-
ables or unlocks the write mechanism of the Rx
FIFO.
31. TMCRDTIMER CONTROL REGISTER
TMCRDTimer Control Register
271072–44
This register controls the operation of the two
M82510 timers. It has no effect when the timers are
configured as baudDrate generators. TGA and TGB
are not reset after command execution.
TGBDTimer-B GateD
This bit serves as a gate for
Timer B operation:
1Denables counting
0Ddisables counting
TGADTimer-A GateD
This bit serves as a gate for
Timer-A operation:
1Denables counting
0Ddisables counting
STBDStart Timer BD
This command triggers timer
B. At terminal count a status bit is set in TMST
(TBEx).
STADStart Timer AD
This command triggers timer
A. At terminal count a status bit is set in TMST
(TAEx).
33
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