
M82510
2. LCRDLINE CONFIGURE REGISTER
LCRDLine Configure Register
271072–15
This register defines the basic configuration of the
serial link.
DLABDDivisor Latch Access BitD
This bit, when
set, allows access to the Divisor Count registers
BAL,BAH;BBL,BBH registers.
SBKDSet Break BitD
This bit will force the TxD pin
low. The TxD pin will remain low (regardless of all
activities) until this bit is reset.
PM2DPM0DParity Mode BitsD
These three bits
combine with the SPF bit of the Transmit Mode reg-
ister to define the various parity modes. See Table
12.
Table 12. Parity Modes
PM0
SPF
PM2
PM1
Function
0
1
1
1
1
1
X
0
0
0
0
1
X
0
0
1
1
0
X
0
1
0
1
0
No Parity
Odd Parity
Even Parity
High Parity
Low Parity
Software Parity
SBLODStop Bit LengthD
This bit, together with
SBL1 and SBL2 bits of the Transmit Mode register,
defines the Stop-bit lengths for transmission. The Rx
machine can identify 3/4 stop bit or more. See Table
13.
Table 13. Stop Bit Length
SBL2
SBL1
SBL0
Stop Bit Length
16X
1X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4/4
D
D
1
1
1
1
1
2
6/4 or 8/4
*
3/4
4/4
5/4
6/4
7/4
8/4
*
6/4 if character length is 5 bits; else 8/4
CL0DCL1DCharacter Length BitsD
These bits,
together with the Transmit Mode register bit NBCL,
define the character length. See Table 14.
Table 14. Character Length
NBCL
CL1
CL0
Character Length
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
5 BITS
6 BITS
7 BITS
8 BITS
9 BITS
18