
M82510
1. IMDDINTERNAL MODE REGISTER
IMDDInternal Mode Register
271072–14
This register defines the general device mode of op-
eration. The bit functions are as follows:
7–4:
Reserved
IAM:
Interrupt Acknowledge Mode Bit
0 D Manual acknowledgement of pend-
ing interrupts
1 D Automatic
pending interrupts (upon CPU serv-
ice)
acknowledgement
of
This bit, when set, configures the M82510 for the
automatic acknowledge mode. This causes the
M82510 INT line to go low for two clock cycles upon
service of the interrupt. After two clock cycles it is
then updated. It is useful in the edge triggered mode.
In manual acknowledgement mode the CPU must
explicitly issue a command to clear the INT pin. (The
INT pin then goes low for a minimum of two clock
cycles until another enabled status register bit is
set.)
RFD:
Receive FIFO Depth
0 D Four Bytes
1 D One Byte
This bit configures the depth of the Rx FIFO. With a
FIFO depth of one, the FIFO will act as a 1-byte
buffer to emulate the 8250A.
ULM:
uLAN Mode
0 D Normal Mode
1 D uLAN Mode
This bit, enables the M82510 to recognize and/or
match address using the 9-bit MCS-51 asynchro-
nous protocol.
LEM:
Loopback/Echo Mode Select
This bit selects the mode of loopback operation, or
the mode of echo operation; depending upon which
operation mode is selected by the Modem Control
register bit LC.
In loopback mode (Modem Control register bit
LC
e
1) it selects between local and remote loop-
back.
0 D Local Loopback
1 D Remote Loopback
Inecho mode (Modem Control register bit LC
e
0) it
selects between echo or non-echo operation.
0 D No Echo
1 D Echo Operation
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