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參數資料
| 型號： | MR82510 |
| 廠商： | Intel Corp. |
| 英文描述： | ASYNCHRONOUS SERIAL CONTROLLER |
| 中文描述： | 異步串行控制器 |
| 文件頁數： | 14/40頁 |
| 文件大小： | 463K |
| 代理商： | MR82510 |
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M82510
BANK ZERO 8250A/16450DCOMPATIBLE BANK
Register
7
6
5
4
3
2
1
0
Address Default
TxD (33)
Tx Data
bit 7
Tx Data Tx Data
bit 6
Tx Data
bit 4
Tx Data
bit 3
Tx Data
bit 2
Tx Data
bit 1
Tx Data
bit 0
0
D
bit 5
RxD (35)
Rx Data
bit 7
Rx Data Rx Data
bit 6
Rx Data
bit 4
Rx Data
bit 3
Rx Data
bit 2
Rx Data
bit 1
Rx Data
bit 0
0
D
bit 5
BAL (11)
BRGA LSB Divide Count (DLAB
e
1)
0
02H
BAH (12)
BRGA MSB Divide Count (DLAB
e
1)
1
00H
GER (16)
0
0
Timer
Interrupt
Enable
Tx Machine Modem
Interrupt
Enable
Rx Machine
Interrupt
Enable
Tx FIFO
Interrupt
Enable
Rx FIFO
Interrupt
Enable
1
00H
Interrupt
Enable
GIR/BANK
(21)
0
BANK
Pointer Pointer
bit 1
BANK
0
Active
Block Int
bit 2
Active
Block Int
bit 1
Active
Block Int
bit 0
Interrupt
Pending
2
01H
bit 0
LCR (2)
DLAB
Divisor
Latch
Access bit
Set
Break
Parity
Mode
bit 2
Parity
Mode
bit 1
Parity
Mode
bit 0
Stop bit
Length
bit 0
Character
Length
bit 1
Character
Length
bit 0
3
00H
MCR (32)
0
0
OUT 0
Complement Control bit Complement Complement
Loopback
OUT 2
OUT 1
RTS
Complement Complement
DTR
4
00H
LSR (22)
0
TxM
Idle
Tx FIFO
Interrupt
Break
Detected
Framing
Error
Parity
Error
State (H
x
L) State
Change
in RI
Overrun
Error
Rx FIFO
Int Req
5
60H
MSR (27)
DCD Input RI Input DSR Input
Inverted
Inverted Inverted
CTS Input
Inverted
State
Change
in DCD
State
Change
in CTS
6
00H
Change
in DSR
ACR0 (5)
Address or Control Character Zero
7
00H
BANK ONEDGENERAL WORK BANK
Register
7
6
5
4
3
2
1
0
Address Default
TxD (33)
Tx Data
bit 7
Tx Data Tx Data
bit 6
Tx Data
bit 4
Tx Data
bit 3
Tx Data
bit 2
Tx Data
bit 1
Tx Data
bit 0
0
D
bit 5
RxD (35)
Rx Data
bit 7
Rx Data Rx Data
bit 6
Rx Data
bit 4
Rx Data
bit 3
Rx Data
bit 2
Rx Data
bit 1
Rx Data
bit 0
0
D
bit 5
RxF (24)
D
Rx Char Rx Char
OK
Rx Char
Parity
Error
Address or
Control
Character
Break
Flag
Rx Char
Framing
Error
Ninth
Data bit
of Rx Char
1
D
Noisy
TxF (34)
Address
Marker bit Parity bit of Data Char
Software Ninth bit
0
0
0
0
0
1
D
GIR/BANK
(21)
0
BANK
Pointer
bit 1
BANK
Pointer
bit 0
0
Active
Block Int
bit 2
Active
Block Int
bit 1
Active
Block Int
bit 0
Interrupt
Pending
2
01H
TMST (26)
D
D
Gate B
State
Gate A
State
D
D
Timer B
Expired
Timer A
Expired
3
30H
TMCR (31)
0
0
Trigger
Gate B
Trigger
Gate A
0
0
Start
Timer B
Start
Timer A
3
D
MCR (32)
0
0
OUT 0
Complement Control bit Complement Complement Complement Complement
Loopback OUT 2
OUT 1
RTS
DTR
4
00H
NOTE:
The register number is provided as a reference number for the register description.
14
相關PDF資料 |
PDF描述 |
|---|---|
| MR8251A | PROGRAMMABLE COMMUNICATION INTERFACE |
| MR851G | Axial Lead Fast Recovery Rectifiers |
| MR851RL | Axial Lead Fast Recovery Rectifiers |
| MR851RLG | Axial Lead Fast Recovery Rectifiers |
| MR852G | Axial Lead Fast Recovery Rectifiers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MR82510/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8251A | 制造商:Intel 功能描述: |
| MR8251A/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/R | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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