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參數資料
| 型號： | MR82510 |
| 廠商： | Intel Corp. |
| 英文描述： | ASYNCHRONOUS SERIAL CONTROLLER |
| 中文描述： | 異步串行控制器 |
| 文件頁數： | 28/40頁 |
| 文件大小： | 463K |
| 代理商： | MR82510 |
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M82510
22. LSRDLINE STATUS REGISTER
LSRDLine Status Register
271072–35
This register holds the status of the serial link. It
shares five of its bits with the RST register (BkD, FE,
PE, OE, and RFIR). When this register is read, the
RST register (BITS 1–7) and LSR register (BITS 1–
4) are cleared. This register is provided for compati-
bility with the INS8250A.
TxStDTransmit Machine Status BitD
Same as
TxIR bit of GSR register. If high it indicates that the
Transmit Machine is in Idle State. (Note: Idle may
indicate that the TxM is either empty or disabled.
TFStDTransmit FIFO StatusD
Same as TFIR bit of
GSR. It indicates that the Transmit FIFO level is
equal to or below the Transmit FIFO Threshold.
There are two ways to disable the transmit FIFO
status from being reflected in GIR:
1. Writing a ‘‘0’’ to the TFIE bit of the GER register
2. Dynamically by using the Tx FIFO HOLD IN-
TERRUPT logic. When the Tx FIFO is in the
Hold State, no interrupts are generated regard-
less of the TFIR and TFIE bits.
The Transmit FIFO enters the Hold State when the
CPU reads the GIR register and the source of the
interrupt is Tx FIFO. To Exit, the CPU must drop the
TFIR bit of GSR by writing a character to Tx FIFO, or
drop TFIE bit of GER (Disable Tx FIFO).
BkdDBreak DetectedD
See Bkd bit in RST register
for full explanation. The BkD bit in RST register is
the same as this bit.
FEDFraming Error DetectedD
See FE bit in RST
register for a full explanation. The FE bit in RST reg-
ister is the same as this bit.
PEDParity Error DetectedD
See PE bit in RST
register for full explanation. The PE bit in RST regis-
ter is the same as this bit.
OEDOverrun ErrorD
See OE bit in RST register for
full explanation. The OE bit in RST register is the
same as this bit.
RFIRDReceive FIFO Interrupt RequestD
This bit
is identical to RFIR bit of GSR. It indicates that the
RX FIFO level is above the Rx FIFO Threshold. This
bit is forced LOW during any READ from the Rx
FIFO. A zero written to this bit will acknowledge an
Rx FIFO interrupt.
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相關PDF資料 |
PDF描述 |
|---|---|
| MR8251A | PROGRAMMABLE COMMUNICATION INTERFACE |
| MR851G | Axial Lead Fast Recovery Rectifiers |
| MR851RL | Axial Lead Fast Recovery Rectifiers |
| MR851RLG | Axial Lead Fast Recovery Rectifiers |
| MR852G | Axial Lead Fast Recovery Rectifiers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MR82510/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8251A | 制造商:Intel 功能描述: |
| MR8251A/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/R | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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