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參數資料
| 型號： | MR82510 |
| 廠商： | Intel Corp. |
| 英文描述： | ASYNCHRONOUS SERIAL CONTROLLER |
| 中文描述： | 異步串行控制器 |
| 文件頁數： | 25/40頁 |
| 文件大小： | 463K |
| 代理商： | MR82510 |
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M82510
INTERRUPT/STATUS REGISTERS
The M82510 uses a two layer approach to handle
interrupt and status generation. Device level regis-
ters show the status of the major M82510 functional
block (MODEM, FIFO, Tx MACHINE, Rx MACHINE,
TIMERS, etc.). Each block may be examined by
reading its individual block level registers. Also each
block has interrupt enable/generation logic which
may generate a request to the built-in interrupt con-
troller, the interrupt requests are then resolved on a
priority basis.
Interrupt Masking
The M82510 has a device enable register, GER,
which can be used to enable or mask-out any block
interrupt request. Some of the blocks (Rx Machine,
Modem, Timer) have an enable register associated
with their status register which can be used to mask
out the individual sources within the block. Interrupts
are enabled when programmed high.
16. GERDGENERAL ENABLE REGISTER
GERDGeneral Enable Register
271072–29
This register enables or disables the bits of the GSR
register from being reflected in the GIR register. It
serves as the device enable register and is used to
mask the interrupt requests from any of the M82510
block (See Figure 1).
TIEDTimers Interrupt Enable
TxIEDTransmit Machine Interrupt Enable.
MIEDModem Interrupt Enable.
RxIEDRx Machine Interrupt Enable.
TFIEDTransmit FIFO Interrupt Enable.
RFIEDReceive FIFO Interrupt Enable.
17. RIEDRECEIVE INTERRUPT ENABLE REGISTER
RIEDReceive Interrupt Enable Register
271072–30
This register enables interrupts from the Rx Ma-
chine. It is used to mask out interrupt requests gen-
erated by the status bits of the RST register.
CREDControl/uLAN Address Character Recog-
nition Interrupt Enable.D
Enables Interrupt when
CRF bit of RST register is set.
PCREDProgrammable Control/Address Charac-
ter Match Interrupt Enable.D
Enables Interrupt on
PCRF bit of RST.
BkTeDBreak Termination Interrupt Enable.
BkDEDBreak Detection Interrupt EnableD
En-
able Interrupt on BkD bit of RST.
FEEDFraming Error EnableD
Enable Interrupt on
FE bit of RST.
PEEDParity Error EnableD
Enable Interrupt on PE
bit of RST.
OEEDOverrun Error EnableD
Enable Interrupt on
OE bit of RST.
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相關PDF資料 |
PDF描述 |
|---|---|
| MR8251A | PROGRAMMABLE COMMUNICATION INTERFACE |
| MR851G | Axial Lead Fast Recovery Rectifiers |
| MR851RL | Axial Lead Fast Recovery Rectifiers |
| MR851RLG | Axial Lead Fast Recovery Rectifiers |
| MR852G | Axial Lead Fast Recovery Rectifiers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MR82510/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8251A | 制造商:Intel 功能描述: |
| MR8251A/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/R | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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